Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T4,T5,T1

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	159461348	156606972	0	0
AllClkBypReqTrue_A	159461348	127967	0	0
IoClkBypReqFalse_A	159461348	156528156	0	2415
IoClkBypReqTrue_A	159461348	202353	0	0
LcClkBypAckFalse_A	159461348	156619063	0	0
LcClkBypAckTrue_A	159461348	115876	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	156606972	0	0
T6	176769	176563	0	0
T7	2076	1820	0	0
T8	1170	1093	0	0
T26	1841	1708	0	0
T27	1207	1186	0	0
T28	1195	1127	0	0
T29	1789	1560	0	0
T30	1601	1472	0	0
T31	2442	2301	0	0
T32	1545	1320	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	127967	0	0
T7	2076	215	0	0
T8	1170	0	0	0
T26	1841	75	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	23	0	0
T31	2442	0	0	0
T32	1545	0	0	0
T43	0	71	0	0
T44	1925	173	0	0
T87	0	166	0	0
T88	0	233	0	0
T89	0	44	0	0
T128	0	273	0	0
T129	0	50	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	156528156	0	2415
T6	176769	176561	0	3
T7	2076	1724	0	3
T8	1170	1091	0	3
T26	1841	1781	0	3
T27	1207	1184	0	3
T28	1195	1125	0	3
T29	1789	1558	0	3
T30	1601	1473	0	3
T31	2442	2299	0	3
T32	1545	1259	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	202353	0	0
T7	2076	309	0	0
T8	1170	0	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	20	0	0
T31	2442	0	0	0
T32	1545	59	0	0
T43	0	68	0	0
T44	1925	416	0	0
T87	0	511	0	0
T88	0	425	0	0
T90	0	547	0	0
T91	0	116	0	0
T128	0	496	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	156619063	0	0
T6	176769	176563	0	0
T7	2076	1909	0	0
T8	1170	1093	0	0
T26	1841	1783	0	0
T27	1207	1186	0	0
T28	1195	1127	0	0
T29	1789	1560	0	0
T30	1601	1478	0	0
T31	2442	2301	0	0
T32	1545	1312	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	115876	0	0
T7	2076	126	0	0
T8	1170	0	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	17	0	0
T31	2442	0	0	0
T32	1545	8	0	0
T43	0	23	0	0
T44	1925	124	0	0
T87	0	281	0	0
T88	0	240	0	0
T90	0	199	0	0
T91	0	73	0	0
T128	0	211	0	0