Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1708928668	14942	0	0
TransStop_A	1708928668	7535	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708928668	14942	0	0
T1	0	101	0	0
T2	0	25	0	0
T20	0	18	0	0
T21	0	4	0	0
T24	0	1	0	0
T29	5652	3	0	0
T30	5724	0	0	0
T31	9772	16	0	0
T32	6240	0	0	0
T35	1709	0	0	0
T41	6964	10	0	0
T42	37500	12	0	0
T43	11928	0	0	0
T44	59220	0	0	0
T45	6860	4	0	0
T46	0	4	0	0
T128	164048	0	0	0
T129	4512	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1708928668	7535	0	0
T1	0	48	0	0
T2	0	10	0	0
T20	0	8	0	0
T21	0	4	0	0
T24	0	1	0	0
T29	5652	3	0	0
T30	5724	0	0	0
T31	9772	5	0	0
T32	6240	0	0	0
T35	1709	0	0	0
T41	6964	9	0	0
T42	37500	8	0	0
T43	11928	0	0	0
T44	59220	0	0	0
T45	6860	4	0	0
T46	0	4	0	0
T128	164048	0	0	0
T129	4512	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	427232167	3693	0	0
TransStop_A	427232167	1894	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427232167	3693	0	0
T1	0	23	0	0
T2	0	7	0	0
T20	0	5	0	0
T21	0	1	0	0
T24	0	1	0	0
T31	2443	5	0	0
T32	1560	0	0	0
T35	1709	0	0	0
T41	1741	3	0	0
T42	9375	5	0	0
T43	2982	0	0	0
T44	14805	0	0	0
T45	1715	1	0	0
T46	0	1	0	0
T128	41012	0	0	0
T129	4512	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427232167	1894	0	0
T1	0	14	0	0
T2	0	2	0	0
T20	0	3	0	0
T21	0	1	0	0
T24	0	1	0	0
T31	2443	1	0	0
T32	1560	0	0	0
T35	1709	0	0	0
T41	1741	2	0	0
T42	9375	4	0	0
T43	2982	0	0	0
T44	14805	0	0	0
T45	1715	1	0	0
T46	0	1	0	0
T128	41012	0	0	0
T129	4512	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	427232167	3766	0	0
TransStop_A	427232167	1862	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427232167	3766	0	0
T1	0	29	0	0
T2	0	7	0	0
T20	0	5	0	0
T21	0	1	0	0
T29	1884	1	0	0
T30	1908	0	0	0
T31	2443	5	0	0
T32	1560	0	0	0
T41	1741	1	0	0
T42	9375	2	0	0
T43	2982	0	0	0
T44	14805	0	0	0
T45	1715	1	0	0
T46	0	1	0	0
T128	41012	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427232167	1862	0	0
T1	0	11	0	0
T2	0	3	0	0
T20	0	2	0	0
T21	0	1	0	0
T29	1884	1	0	0
T30	1908	0	0	0
T31	2443	2	0	0
T32	1560	0	0	0
T41	1741	1	0	0
T42	9375	1	0	0
T43	2982	0	0	0
T44	14805	0	0	0
T45	1715	1	0	0
T46	0	1	0	0
T128	41012	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	427232167	3714	0	0
TransStop_A	427232167	1873	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427232167	3714	0	0
T1	0	24	0	0
T2	0	5	0	0
T20	0	3	0	0
T21	0	1	0	0
T29	1884	1	0	0
T30	1908	0	0	0
T31	2443	3	0	0
T32	1560	0	0	0
T41	1741	3	0	0
T42	9375	2	0	0
T43	2982	0	0	0
T44	14805	0	0	0
T45	1715	1	0	0
T46	0	1	0	0
T128	41012	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427232167	1873	0	0
T1	0	12	0	0
T2	0	3	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	1884	1	0	0
T30	1908	0	0	0
T31	2443	1	0	0
T32	1560	0	0	0
T41	1741	3	0	0
T42	9375	1	0	0
T43	2982	0	0	0
T44	14805	0	0	0
T45	1715	1	0	0
T46	0	1	0	0
T128	41012	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	427232167	3769	0	0
TransStop_A	427232167	1906	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427232167	3769	0	0
T1	0	25	0	0
T2	0	6	0	0
T20	0	5	0	0
T21	0	1	0	0
T29	1884	1	0	0
T30	1908	0	0	0
T31	2443	3	0	0
T32	1560	0	0	0
T41	1741	3	0	0
T42	9375	3	0	0
T43	2982	0	0	0
T44	14805	0	0	0
T45	1715	1	0	0
T46	0	1	0	0
T128	41012	0	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427232167	1906	0	0
T1	0	11	0	0
T2	0	2	0	0
T20	0	2	0	0
T21	0	1	0	0
T29	1884	1	0	0
T30	1908	0	0	0
T31	2443	1	0	0
T32	1560	0	0	0
T41	1741	3	0	0
T42	9375	2	0	0
T43	2982	0	0	0
T44	14805	0	0	0
T45	1715	1	0	0
T46	0	1	0	0
T128	41012	0	0	0