Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	159461348	18574513	0	55

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	18574513	0	55
T1	808721	118317	0	0
T2	193305	35192	0	0
T3	0	55763	0	0
T11	0	21487	0	1
T12	0	3825	0	1
T13	0	25512	0	0
T14	0	83915	0	0
T15	0	7027	0	1
T16	0	317771	0	0
T18	2241	0	0	0
T19	33440	882	0	1
T20	1777	0	0	0
T21	2472	0	0	0
T22	19232	0	0	0
T23	98261	0	0	0
T24	2123	0	0	0
T25	1004	0	0	0
T33	0	0	0	1
T63	0	0	0	1
T96	0	0	0	1
T130	0	0	0	1
T131	0	0	0	1
T132	0	0	0	1