Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	160411281	5444267	0	0
clk_enables_rd_A	160411281	25709	0	0
clk_hints_rd_A	160411281	23322	0	0
extclk_ctrl_rd_A	160411281	28809	0	0
extclk_ctrl_regwen_rd_A	160411281	21782	0	0
jitter_enable_rd_A	160411281	32626	0	0
jitter_regwen_rd_A	160411281	23866	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	5444267	0	0
T3	163484	79220	0	0
T11	361271	0	0	0
T12	12444	0	0	0
T13	125357	0	0	0
T14	278133	93106	0	0
T15	42155	0	0	0
T16	0	144933	0	0
T17	0	61046	0	0
T38	0	55752	0	0
T78	0	39144	0	0
T79	0	115958	0	0
T80	0	77849	0	0
T81	0	82189	0	0
T82	0	87735	0	0
T83	1776	0	0	0
T84	1446	0	0	0
T85	107326	0	0	0
T86	1544	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	25709	0	0
T2	193305	0	0	0
T3	163484	0	0	0
T11	361271	0	0	0
T12	12444	0	0	0
T13	125357	12	0	0
T21	2472	5	0	0
T22	19232	0	0	0
T23	98261	0	0	0
T24	2123	0	0	0
T25	1004	0	0	0
T34	0	6	0	0
T54	0	2	0	0
T80	0	3169	0	0
T153	0	5	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	4	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	23322	0	0
T2	193305	0	0	0
T3	163484	0	0	0
T11	361271	0	0	0
T12	12444	0	0	0
T13	125357	8	0	0
T21	2472	2	0	0
T22	19232	0	0	0
T23	98261	0	0	0
T24	2123	0	0	0
T25	1004	0	0	0
T34	0	6	0	0
T80	0	2576	0	0
T153	0	2	0	0
T156	0	5	0	0
T158	0	3	0	0
T159	0	4	0	0
T160	0	1845	0	0
T161	0	1	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	28809	0	0
T4	0	33	0	0
T13	0	4	0	0
T32	1545	1	0	0
T35	1640	0	0	0
T36	841	0	0	0
T41	1670	0	0	0
T42	1969	0	0	0
T43	1431	0	0	0
T44	1925	0	0	0
T45	1714	0	0	0
T87	0	50	0	0
T90	0	49	0	0
T93	0	103	0	0
T128	2050	37	0	0
T129	1218	0	0	0
T162	0	50	0	0
T163	0	30	0	0
T164	0	55	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	21782	0	0
T4	16174	9	0	0
T5	39876	0	0	0
T37	1796	0	0	0
T46	1892	0	0	0
T80	0	2586	0	0
T87	2668	0	0	0
T88	2255	0	0	0
T89	1617	0	0	0
T90	2907	0	0	0
T91	1166	0	0	0
T92	1613	0	0	0
T93	0	32	0	0
T127	0	6	0	0
T165	0	33	0	0
T166	0	15	0	0
T167	0	21	0	0
T168	0	19	0	0
T169	0	33	0	0
T170	0	57	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	32626	0	0
T2	193305	0	0	0
T3	163484	0	0	0
T11	361271	0	0	0
T12	12444	0	0	0
T13	125357	121	0	0
T21	2472	112	0	0
T22	19232	0	0	0
T23	98261	0	0	0
T24	2123	100	0	0
T25	1004	0	0	0
T34	0	80	0	0
T54	0	114	0	0
T80	0	4245	0	0
T153	0	110	0	0
T154	0	76	0	0
T155	0	66	0	0
T158	0	120	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	23866	0	0
T74	0	58	0	0
T80	273029	2900	0	0
T99	0	32	0	0
T102	0	116	0	0
T113	0	64	0	0
T127	4923	0	0	0
T160	0	2047	0	0
T166	46351	0	0	0
T171	0	1073	0	0
T172	0	5579	0	0
T173	0	5869	0	0
T174	0	3629	0	0
T175	651	0	0	0
T176	2306	0	0	0
T177	832	0	0	0
T178	1277	0	0	0
T179	1703	0	0	0
T180	2090	0	0	0
T181	2578	0	0	0