Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T5,T3
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1604112810	1467514	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1604112810	272143	0	0
SrcBusyKnown_A	1604112810	1575864350	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604112810	1467514	0	0
T1	0	11560	0	0
T2	0	2695	0	0
T3	0	5128	0	0
T4	0	845	0	0
T5	0	2074	0	0
T6	1767690	2304	0	0
T7	20760	0	0	0
T8	11700	0	0	0
T11	0	6003	0	0
T19	0	614	0	0
T22	0	585	0	0
T23	0	1371	0	0
T26	18410	0	0	0
T27	12070	0	0	0
T28	11950	0	0	0
T29	17890	0	0	0
T30	16010	0	0	0
T31	24420	0	0	0
T32	15450	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T6	954744	953546	0	0
T7	55584	54676	0	0
T8	13294	12354	0	0
T26	48736	47418	0	0
T27	61200	60162	0	0
T28	26398	24882	0	0
T29	11762	10382	0	0
T30	12050	11310	0	0
T31	15400	14550	0	0
T32	9708	8442	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604112810	272143	0	0
T1	0	1400	0	0
T2	0	320	0	0
T3	0	1540	0	0
T4	0	234	0	0
T5	0	579	0	0
T6	1767690	300	0	0
T7	20760	0	0	0
T8	11700	0	0	0
T11	0	1180	0	0
T19	0	120	0	0
T22	0	220	0	0
T23	0	160	0	0
T26	18410	0	0	0
T27	12070	0	0	0
T28	11950	0	0	0
T29	17890	0	0	0
T30	16010	0	0	0
T31	24420	0	0	0
T32	15450	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604112810	1575864350	0	0
T6	1767690	1765640	0	0
T7	20760	20360	0	0
T8	11700	10940	0	0
T26	18410	17840	0	0
T27	12070	11870	0	0
T28	11950	11280	0	0
T29	17890	15610	0	0
T30	16010	14960	0	0
T31	24420	23020	0	0
T32	15450	13210	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160411281	90346	0	0
DstReqKnown_A	402003890	397349828	0	0
SrcAckBusyChk_A	160411281	24387	0	0
SrcBusyKnown_A	160411281	157586435	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	90346	0	0
T1	0	827	0	0
T2	0	194	0	0
T3	0	368	0	0
T4	0	43	0	0
T5	0	108	0	0
T6	176769	147	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	427	0	0
T19	0	42	0	0
T22	0	52	0	0
T23	0	84	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402003890	397349828	0	0
T6	128856	128653	0	0
T7	8308	8145	0	0
T8	2019	1870	0	0
T26	7367	7136	0	0
T27	8971	8795	0	0
T28	4205	3947	0	0
T29	1808	1577	0	0
T30	1831	1710	0	0
T31	2345	2210	0	0
T32	1498	1281	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	24387	0	0
T1	0	140	0	0
T2	0	32	0	0
T3	0	151	0	0
T4	0	16	0	0
T5	0	40	0	0
T6	176769	30	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	118	0	0
T19	0	12	0	0
T22	0	22	0	0
T23	0	16	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	157586435	0	0
T6	176769	176564	0	0
T7	2076	2036	0	0
T8	1170	1094	0	0
T26	1841	1784	0	0
T27	1207	1187	0	0
T28	1195	1128	0	0
T29	1789	1561	0	0
T30	1601	1496	0	0
T31	2442	2302	0	0
T32	1545	1321	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160411281	131343	0	0
DstReqKnown_A	200501698	199353902	0	0
SrcAckBusyChk_A	160411281	24387	0	0
SrcBusyKnown_A	160411281	157586435	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	131343	0	0
T1	0	1181	0	0
T2	0	277	0	0
T3	0	520	0	0
T4	0	59	0	0
T5	0	147	0	0
T6	176769	231	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	601	0	0
T19	0	61	0	0
T22	0	53	0	0
T23	0	136	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200501698	199353902	0	0
T6	64382	64327	0	0
T7	4452	4424	0	0
T8	997	935	0	0
T26	3761	3713	0	0
T27	4446	4398	0	0
T28	2042	1973	0	0
T29	857	788	0	0
T30	914	873	0	0
T31	1160	1105	0	0
T32	699	644	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	24387	0	0
T1	0	140	0	0
T2	0	32	0	0
T3	0	151	0	0
T4	0	16	0	0
T5	0	40	0	0
T6	176769	30	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	118	0	0
T19	0	12	0	0
T22	0	22	0	0
T23	0	16	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	157586435	0	0
T6	176769	176564	0	0
T7	2076	2036	0	0
T8	1170	1094	0	0
T26	1841	1784	0	0
T27	1207	1187	0	0
T28	1195	1128	0	0
T29	1789	1561	0	0
T30	1601	1496	0	0
T31	2442	2302	0	0
T32	1545	1321	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160411281	211257	0	0
DstReqKnown_A	100250231	99676400	0	0
SrcAckBusyChk_A	160411281	24387	0	0
SrcBusyKnown_A	160411281	157586435	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	211257	0	0
T1	0	2000	0	0
T2	0	462	0	0
T3	0	735	0	0
T4	0	85	0	0
T5	0	207	0	0
T6	176769	407	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	967	0	0
T19	0	103	0	0
T22	0	77	0	0
T23	0	233	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100250231	99676400	0	0
T6	32191	32163	0	0
T7	2226	2212	0	0
T8	499	468	0	0
T26	1881	1857	0	0
T27	2223	2199	0	0
T28	1021	987	0	0
T29	429	395	0	0
T30	457	436	0	0
T31	580	552	0	0
T32	350	323	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	24387	0	0
T1	0	140	0	0
T2	0	32	0	0
T3	0	151	0	0
T4	0	16	0	0
T5	0	40	0	0
T6	176769	30	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	118	0	0
T19	0	12	0	0
T22	0	22	0	0
T23	0	16	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	157586435	0	0
T6	176769	176564	0	0
T7	2076	2036	0	0
T8	1170	1094	0	0
T26	1841	1784	0	0
T27	1207	1187	0	0
T28	1195	1128	0	0
T29	1789	1561	0	0
T30	1601	1496	0	0
T31	2442	2302	0	0
T32	1545	1321	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160411281	88429	0	0
DstReqKnown_A	429892831	424970121	0	0
SrcAckBusyChk_A	160411281	24387	0	0
SrcBusyKnown_A	160411281	157586435	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	88429	0	0
T1	0	670	0	0
T2	0	158	0	0
T3	0	368	0	0
T4	0	42	0	0
T5	0	103	0	0
T6	176769	143	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	411	0	0
T19	0	42	0	0
T22	0	52	0	0
T23	0	98	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429892831	424970121	0	0
T6	170231	170019	0	0
T7	8653	8484	0	0
T8	2097	1943	0	0
T26	7675	7435	0	0
T27	10288	10105	0	0
T28	3888	3619	0	0
T29	1883	1642	0	0
T30	1907	1781	0	0
T31	2442	2302	0	0
T32	1559	1333	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	24387	0	0
T1	0	140	0	0
T2	0	32	0	0
T3	0	151	0	0
T4	0	16	0	0
T5	0	40	0	0
T6	176769	30	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	118	0	0
T19	0	12	0	0
T22	0	22	0	0
T23	0	16	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	157586435	0	0
T6	176769	176564	0	0
T7	2076	2036	0	0
T8	1170	1094	0	0
T26	1841	1784	0	0
T27	1207	1187	0	0
T28	1195	1128	0	0
T29	1789	1561	0	0
T30	1601	1496	0	0
T31	2442	2302	0	0
T32	1545	1321	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160411281	128511	0	0
DstReqKnown_A	206381722	204024384	0	0
SrcAckBusyChk_A	160411281	23887	0	0
SrcBusyKnown_A	160411281	157586435	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	128511	0	0
T1	0	1093	0	0
T2	0	261	0	0
T3	0	519	0	0
T4	0	48	0	0
T5	0	95	0	0
T6	176769	231	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	595	0	0
T19	0	60	0	0
T22	0	54	0	0
T23	0	134	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206381722	204024384	0	0
T6	81712	81611	0	0
T7	4153	4073	0	0
T8	1035	961	0	0
T26	3684	3568	0	0
T27	4672	4584	0	0
T28	2043	1915	0	0
T29	904	789	0	0
T30	916	855	0	0
T31	1173	1106	0	0
T32	748	640	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	23887	0	0
T1	0	140	0	0
T2	0	32	0	0
T3	0	151	0	0
T4	0	10	0	0
T5	0	20	0	0
T6	176769	30	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	118	0	0
T19	0	12	0	0
T22	0	22	0	0
T23	0	16	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	157586435	0	0
T6	176769	176564	0	0
T7	2076	2036	0	0
T8	1170	1094	0	0
T26	1841	1784	0	0
T27	1207	1187	0	0
T28	1195	1128	0	0
T29	1789	1561	0	0
T30	1601	1496	0	0
T31	2442	2302	0	0
T32	1545	1321	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T5,T3
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160411281	113275	0	0
DstReqKnown_A	402003890	397349828	0	0
SrcAckBusyChk_A	160411281	30280	0	0
SrcBusyKnown_A	160411281	157586435	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	113275	0	0
T1	0	826	0	0
T2	0	194	0	0
T3	0	384	0	0
T4	0	85	0	0
T5	0	212	0	0
T6	176769	146	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	421	0	0
T19	0	42	0	0
T22	0	52	0	0
T23	0	84	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402003890	397349828	0	0
T6	128856	128653	0	0
T7	8308	8145	0	0
T8	2019	1870	0	0
T26	7367	7136	0	0
T27	8971	8795	0	0
T28	4205	3947	0	0
T29	1808	1577	0	0
T30	1831	1710	0	0
T31	2345	2210	0	0
T32	1498	1281	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	30280	0	0
T1	0	140	0	0
T2	0	32	0	0
T3	0	157	0	0
T4	0	32	0	0
T5	0	80	0	0
T6	176769	30	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	118	0	0
T19	0	12	0	0
T22	0	22	0	0
T23	0	16	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	157586435	0	0
T6	176769	176564	0	0
T7	2076	2036	0	0
T8	1170	1094	0	0
T26	1841	1784	0	0
T27	1207	1187	0	0
T28	1195	1128	0	0
T29	1789	1561	0	0
T30	1601	1496	0	0
T31	2442	2302	0	0
T32	1545	1321	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T5,T3
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160411281	164534	0	0
DstReqKnown_A	200501698	199353902	0	0
SrcAckBusyChk_A	160411281	30235	0	0
SrcBusyKnown_A	160411281	157586435	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	164534	0	0
T1	0	1175	0	0
T2	0	270	0	0
T3	0	541	0	0
T4	0	115	0	0
T5	0	289	0	0
T6	176769	230	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	602	0	0
T19	0	62	0	0
T22	0	58	0	0
T23	0	138	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200501698	199353902	0	0
T6	64382	64327	0	0
T7	4452	4424	0	0
T8	997	935	0	0
T26	3761	3713	0	0
T27	4446	4398	0	0
T28	2042	1973	0	0
T29	857	788	0	0
T30	914	873	0	0
T31	1160	1105	0	0
T32	699	644	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	30235	0	0
T1	0	140	0	0
T2	0	32	0	0
T3	0	157	0	0
T4	0	32	0	0
T5	0	80	0	0
T6	176769	30	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	118	0	0
T19	0	12	0	0
T22	0	22	0	0
T23	0	16	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	157586435	0	0
T6	176769	176564	0	0
T7	2076	2036	0	0
T8	1170	1094	0	0
T26	1841	1784	0	0
T27	1207	1187	0	0
T28	1195	1128	0	0
T29	1789	1561	0	0
T30	1601	1496	0	0
T31	2442	2302	0	0
T32	1545	1321	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T5,T3
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160411281	265806	0	0
DstReqKnown_A	100250231	99676400	0	0
SrcAckBusyChk_A	160411281	30094	0	0
SrcBusyKnown_A	160411281	157586435	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	265806	0	0
T1	0	2019	0	0
T2	0	460	0	0
T3	0	768	0	0
T4	0	167	0	0
T5	0	419	0	0
T6	176769	398	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	968	0	0
T19	0	100	0	0
T22	0	80	0	0
T23	0	234	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100250231	99676400	0	0
T6	32191	32163	0	0
T7	2226	2212	0	0
T8	499	468	0	0
T26	1881	1857	0	0
T27	2223	2199	0	0
T28	1021	987	0	0
T29	429	395	0	0
T30	457	436	0	0
T31	580	552	0	0
T32	350	323	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	30094	0	0
T1	0	140	0	0
T2	0	32	0	0
T3	0	157	0	0
T4	0	32	0	0
T5	0	80	0	0
T6	176769	30	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	118	0	0
T19	0	12	0	0
T22	0	22	0	0
T23	0	16	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	157586435	0	0
T6	176769	176564	0	0
T7	2076	2036	0	0
T8	1170	1094	0	0
T26	1841	1784	0	0
T27	1207	1187	0	0
T28	1195	1128	0	0
T29	1789	1561	0	0
T30	1601	1496	0	0
T31	2442	2302	0	0
T32	1545	1321	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T5,T3
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160411281	111192	0	0
DstReqKnown_A	429892831	424970121	0	0
SrcAckBusyChk_A	160411281	30272	0	0
SrcBusyKnown_A	160411281	157586435	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	111192	0	0
T1	0	669	0	0
T2	0	159	0	0
T3	0	384	0	0
T4	0	82	0	0
T5	0	205	0	0
T6	176769	142	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	411	0	0
T19	0	42	0	0
T22	0	52	0	0
T23	0	98	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429892831	424970121	0	0
T6	170231	170019	0	0
T7	8653	8484	0	0
T8	2097	1943	0	0
T26	7675	7435	0	0
T27	10288	10105	0	0
T28	3888	3619	0	0
T29	1883	1642	0	0
T30	1907	1781	0	0
T31	2442	2302	0	0
T32	1559	1333	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	30272	0	0
T1	0	140	0	0
T2	0	32	0	0
T3	0	157	0	0
T4	0	32	0	0
T5	0	80	0	0
T6	176769	30	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	118	0	0
T19	0	12	0	0
T22	0	22	0	0
T23	0	16	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	157586435	0	0
T6	176769	176564	0	0
T7	2076	2036	0	0
T8	1170	1094	0	0
T26	1841	1784	0	0
T27	1207	1187	0	0
T28	1195	1128	0	0
T29	1789	1561	0	0
T30	1601	1496	0	0
T31	2442	2302	0	0
T32	1545	1321	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T5,T3
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	160411281	162821	0	0
DstReqKnown_A	206381722	204024384	0	0
SrcAckBusyChk_A	160411281	29827	0	0
SrcBusyKnown_A	160411281	157586435	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	162821	0	0
T1	0	1100	0	0
T2	0	260	0	0
T3	0	541	0	0
T4	0	119	0	0
T5	0	289	0	0
T6	176769	229	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	600	0	0
T19	0	60	0	0
T22	0	55	0	0
T23	0	132	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206381722	204024384	0	0
T6	81712	81611	0	0
T7	4153	4073	0	0
T8	1035	961	0	0
T26	3684	3568	0	0
T27	4672	4584	0	0
T28	2043	1915	0	0
T29	904	789	0	0
T30	916	855	0	0
T31	1173	1106	0	0
T32	748	640	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	29827	0	0
T1	0	140	0	0
T2	0	32	0	0
T3	0	157	0	0
T4	0	32	0	0
T5	0	79	0	0
T6	176769	30	0	0
T7	2076	0	0	0
T8	1170	0	0	0
T11	0	118	0	0
T19	0	12	0	0
T22	0	22	0	0
T23	0	16	0	0
T26	1841	0	0	0
T27	1207	0	0	0
T28	1195	0	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160411281	157586435	0	0
T6	176769	176564	0	0
T7	2076	2036	0	0
T8	1170	1094	0	0
T26	1841	1784	0	0
T27	1207	1187	0	0
T28	1195	1128	0	0
T29	1789	1561	0	0
T30	1601	1496	0	0
T31	2442	2302	0	0
T32	1545	1321	0	0