SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.63 | 100.00 | 93.15 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.63 | 100.00 | 93.15 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T26,T30 |
1 | 0 | Covered | T7,T30,T44 |
1 | 1 | Covered | T7,T26,T30 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 399449754 | 4451 | 0 | 0 |
g_div2.Div2Whole_A | 399449754 | 5308 | 0 | 0 |
g_div4.Div4Stepped_A | 199269093 | 4358 | 0 | 0 |
g_div4.Div4Whole_A | 199269093 | 4970 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 399449754 | 4451 | 0 | 0 |
T7 | 8308 | 6 | 0 | 0 |
T8 | 2019 | 0 | 0 | 0 |
T26 | 7368 | 4 | 0 | 0 |
T27 | 8971 | 0 | 0 | 0 |
T28 | 4206 | 0 | 0 | 0 |
T29 | 1808 | 0 | 0 | 0 |
T30 | 1831 | 1 | 0 | 0 |
T31 | 2345 | 0 | 0 | 0 |
T32 | 1498 | 0 | 0 | 0 |
T43 | 0 | 1 | 0 | 0 |
T44 | 14212 | 7 | 0 | 0 |
T87 | 0 | 8 | 0 | 0 |
T88 | 0 | 9 | 0 | 0 |
T89 | 0 | 1 | 0 | 0 |
T128 | 0 | 9 | 0 | 0 |
T129 | 0 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 399449754 | 5308 | 0 | 0 |
T7 | 8308 | 8 | 0 | 0 |
T8 | 2019 | 0 | 0 | 0 |
T26 | 7368 | 5 | 0 | 0 |
T27 | 8971 | 0 | 0 | 0 |
T28 | 4206 | 0 | 0 | 0 |
T29 | 1808 | 0 | 0 | 0 |
T30 | 1831 | 4 | 0 | 0 |
T31 | 2345 | 0 | 0 | 0 |
T32 | 1498 | 1 | 0 | 0 |
T43 | 0 | 2 | 0 | 0 |
T44 | 14212 | 7 | 0 | 0 |
T87 | 0 | 9 | 0 | 0 |
T88 | 0 | 9 | 0 | 0 |
T128 | 0 | 9 | 0 | 0 |
T129 | 0 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 199269093 | 4358 | 0 | 0 |
T7 | 4453 | 6 | 0 | 0 |
T8 | 998 | 0 | 0 | 0 |
T26 | 3762 | 4 | 0 | 0 |
T27 | 4446 | 0 | 0 | 0 |
T28 | 2043 | 0 | 0 | 0 |
T29 | 858 | 0 | 0 | 0 |
T30 | 915 | 0 | 0 | 0 |
T31 | 1161 | 0 | 0 | 0 |
T32 | 700 | 0 | 0 | 0 |
T43 | 0 | 1 | 0 | 0 |
T44 | 7573 | 7 | 0 | 0 |
T87 | 0 | 8 | 0 | 0 |
T88 | 0 | 9 | 0 | 0 |
T89 | 0 | 1 | 0 | 0 |
T90 | 0 | 7 | 0 | 0 |
T128 | 0 | 9 | 0 | 0 |
T129 | 0 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 199269093 | 4970 | 0 | 0 |
T7 | 4453 | 8 | 0 | 0 |
T8 | 998 | 0 | 0 | 0 |
T26 | 3762 | 5 | 0 | 0 |
T27 | 4446 | 0 | 0 | 0 |
T28 | 2043 | 0 | 0 | 0 |
T29 | 858 | 0 | 0 | 0 |
T30 | 915 | 4 | 0 | 0 |
T31 | 1161 | 0 | 0 | 0 |
T32 | 700 | 1 | 0 | 0 |
T43 | 0 | 2 | 0 | 0 |
T44 | 7573 | 6 | 0 | 0 |
T87 | 0 | 9 | 0 | 0 |
T88 | 0 | 9 | 0 | 0 |
T128 | 0 | 9 | 0 | 0 |
T129 | 0 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T26,T30 |
1 | 0 | Covered | T7,T30,T44 |
1 | 1 | Covered | T7,T26,T30 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 399449754 | 4451 | 0 | 0 |
g_div2.Div2Whole_A | 399449754 | 5308 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 399449754 | 4451 | 0 | 0 |
T7 | 8308 | 6 | 0 | 0 |
T8 | 2019 | 0 | 0 | 0 |
T26 | 7368 | 4 | 0 | 0 |
T27 | 8971 | 0 | 0 | 0 |
T28 | 4206 | 0 | 0 | 0 |
T29 | 1808 | 0 | 0 | 0 |
T30 | 1831 | 1 | 0 | 0 |
T31 | 2345 | 0 | 0 | 0 |
T32 | 1498 | 0 | 0 | 0 |
T43 | 0 | 1 | 0 | 0 |
T44 | 14212 | 7 | 0 | 0 |
T87 | 0 | 8 | 0 | 0 |
T88 | 0 | 9 | 0 | 0 |
T89 | 0 | 1 | 0 | 0 |
T128 | 0 | 9 | 0 | 0 |
T129 | 0 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 399449754 | 5308 | 0 | 0 |
T7 | 8308 | 8 | 0 | 0 |
T8 | 2019 | 0 | 0 | 0 |
T26 | 7368 | 5 | 0 | 0 |
T27 | 8971 | 0 | 0 | 0 |
T28 | 4206 | 0 | 0 | 0 |
T29 | 1808 | 0 | 0 | 0 |
T30 | 1831 | 4 | 0 | 0 |
T31 | 2345 | 0 | 0 | 0 |
T32 | 1498 | 1 | 0 | 0 |
T43 | 0 | 2 | 0 | 0 |
T44 | 14212 | 7 | 0 | 0 |
T87 | 0 | 9 | 0 | 0 |
T88 | 0 | 9 | 0 | 0 |
T128 | 0 | 9 | 0 | 0 |
T129 | 0 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T26,T30 |
1 | 0 | Covered | T7,T30,T44 |
1 | 1 | Covered | T7,T26,T30 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 199269093 | 4358 | 0 | 0 |
g_div4.Div4Whole_A | 199269093 | 4970 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 199269093 | 4358 | 0 | 0 |
T7 | 4453 | 6 | 0 | 0 |
T8 | 998 | 0 | 0 | 0 |
T26 | 3762 | 4 | 0 | 0 |
T27 | 4446 | 0 | 0 | 0 |
T28 | 2043 | 0 | 0 | 0 |
T29 | 858 | 0 | 0 | 0 |
T30 | 915 | 0 | 0 | 0 |
T31 | 1161 | 0 | 0 | 0 |
T32 | 700 | 0 | 0 | 0 |
T43 | 0 | 1 | 0 | 0 |
T44 | 7573 | 7 | 0 | 0 |
T87 | 0 | 8 | 0 | 0 |
T88 | 0 | 9 | 0 | 0 |
T89 | 0 | 1 | 0 | 0 |
T90 | 0 | 7 | 0 | 0 |
T128 | 0 | 9 | 0 | 0 |
T129 | 0 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 199269093 | 4970 | 0 | 0 |
T7 | 4453 | 8 | 0 | 0 |
T8 | 998 | 0 | 0 | 0 |
T26 | 3762 | 5 | 0 | 0 |
T27 | 4446 | 0 | 0 | 0 |
T28 | 2043 | 0 | 0 | 0 |
T29 | 858 | 0 | 0 | 0 |
T30 | 915 | 4 | 0 | 0 |
T31 | 1161 | 0 | 0 | 0 |
T32 | 700 | 1 | 0 | 0 |
T43 | 0 | 2 | 0 | 0 |
T44 | 7573 | 6 | 0 | 0 |
T87 | 0 | 9 | 0 | 0 |
T88 | 0 | 9 | 0 | 0 |
T128 | 0 | 9 | 0 | 0 |
T129 | 0 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |