Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T26,T30
10CoveredT7,T30,T44
11CoveredT7,T26,T30

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 399449754 4451 0 0
g_div2.Div2Whole_A 399449754 5308 0 0
g_div4.Div4Stepped_A 199269093 4358 0 0
g_div4.Div4Whole_A 199269093 4970 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 399449754 4451 0 0
T7 8308 6 0 0
T8 2019 0 0 0
T26 7368 4 0 0
T27 8971 0 0 0
T28 4206 0 0 0
T29 1808 0 0 0
T30 1831 1 0 0
T31 2345 0 0 0
T32 1498 0 0 0
T43 0 1 0 0
T44 14212 7 0 0
T87 0 8 0 0
T88 0 9 0 0
T89 0 1 0 0
T128 0 9 0 0
T129 0 1 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 399449754 5308 0 0
T7 8308 8 0 0
T8 2019 0 0 0
T26 7368 5 0 0
T27 8971 0 0 0
T28 4206 0 0 0
T29 1808 0 0 0
T30 1831 4 0 0
T31 2345 0 0 0
T32 1498 1 0 0
T43 0 2 0 0
T44 14212 7 0 0
T87 0 9 0 0
T88 0 9 0 0
T128 0 9 0 0
T129 0 1 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 199269093 4358 0 0
T7 4453 6 0 0
T8 998 0 0 0
T26 3762 4 0 0
T27 4446 0 0 0
T28 2043 0 0 0
T29 858 0 0 0
T30 915 0 0 0
T31 1161 0 0 0
T32 700 0 0 0
T43 0 1 0 0
T44 7573 7 0 0
T87 0 8 0 0
T88 0 9 0 0
T89 0 1 0 0
T90 0 7 0 0
T128 0 9 0 0
T129 0 1 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 199269093 4970 0 0
T7 4453 8 0 0
T8 998 0 0 0
T26 3762 5 0 0
T27 4446 0 0 0
T28 2043 0 0 0
T29 858 0 0 0
T30 915 4 0 0
T31 1161 0 0 0
T32 700 1 0 0
T43 0 2 0 0
T44 7573 6 0 0
T87 0 9 0 0
T88 0 9 0 0
T128 0 9 0 0
T129 0 1 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T26,T30
10CoveredT7,T30,T44
11CoveredT7,T26,T30

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 399449754 4451 0 0
g_div2.Div2Whole_A 399449754 5308 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 399449754 4451 0 0
T7 8308 6 0 0
T8 2019 0 0 0
T26 7368 4 0 0
T27 8971 0 0 0
T28 4206 0 0 0
T29 1808 0 0 0
T30 1831 1 0 0
T31 2345 0 0 0
T32 1498 0 0 0
T43 0 1 0 0
T44 14212 7 0 0
T87 0 8 0 0
T88 0 9 0 0
T89 0 1 0 0
T128 0 9 0 0
T129 0 1 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 399449754 5308 0 0
T7 8308 8 0 0
T8 2019 0 0 0
T26 7368 5 0 0
T27 8971 0 0 0
T28 4206 0 0 0
T29 1808 0 0 0
T30 1831 4 0 0
T31 2345 0 0 0
T32 1498 1 0 0
T43 0 2 0 0
T44 14212 7 0 0
T87 0 9 0 0
T88 0 9 0 0
T128 0 9 0 0
T129 0 1 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T26,T30
10CoveredT7,T30,T44
11CoveredT7,T26,T30

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 199269093 4358 0 0
g_div4.Div4Whole_A 199269093 4970 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 199269093 4358 0 0
T7 4453 6 0 0
T8 998 0 0 0
T26 3762 4 0 0
T27 4446 0 0 0
T28 2043 0 0 0
T29 858 0 0 0
T30 915 0 0 0
T31 1161 0 0 0
T32 700 0 0 0
T43 0 1 0 0
T44 7573 7 0 0
T87 0 8 0 0
T88 0 9 0 0
T89 0 1 0 0
T90 0 7 0 0
T128 0 9 0 0
T129 0 1 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 199269093 4970 0 0
T7 4453 8 0 0
T8 998 0 0 0
T26 3762 5 0 0
T27 4446 0 0 0
T28 2043 0 0 0
T29 858 0 0 0
T30 915 4 0 0
T31 1161 0 0 0
T32 700 1 0 0
T43 0 2 0 0
T44 7573 6 0 0
T87 0 9 0 0
T88 0 9 0 0
T128 0 9 0 0
T129 0 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%