Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	159461348	145	0	0
IoStatusRise_A	159461348	145	0	0
MainStatusFall_A	159461348	148	0	0
MainStatusRise_A	159461348	148	0	0
UsbStatusFall_A	159461348	155	0	0
UsbStatusRise_A	159461348	155	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	145	0	0
T8	1170	7	0	0
T26	1841	0	0	0
T27	1207	3	0	0
T28	1195	7	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0
T43	1431	0	0	0
T44	1925	0	0	0
T57	0	3	0	0
T60	0	5	0	0
T62	0	1	0	0
T84	0	4	0	0
T86	0	2	0	0
T182	0	3	0	0
T183	0	4	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	145	0	0
T8	1170	7	0	0
T26	1841	0	0	0
T27	1207	3	0	0
T28	1195	7	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0
T43	1431	0	0	0
T44	1925	0	0	0
T57	0	3	0	0
T60	0	5	0	0
T62	0	1	0	0
T84	0	4	0	0
T86	0	2	0	0
T182	0	3	0	0
T183	0	4	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	148	0	0
T8	1170	4	0	0
T26	1841	0	0	0
T27	1207	6	0	0
T28	1195	5	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0
T43	1431	0	0	0
T44	1925	0	0	0
T60	0	3	0	0
T62	0	1	0	0
T84	0	2	0	0
T86	0	2	0	0
T178	0	2	0	0
T182	0	3	0	0
T183	0	2	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	148	0	0
T8	1170	4	0	0
T26	1841	0	0	0
T27	1207	6	0	0
T28	1195	5	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0
T43	1431	0	0	0
T44	1925	0	0	0
T60	0	3	0	0
T62	0	1	0	0
T84	0	2	0	0
T86	0	2	0	0
T178	0	2	0	0
T182	0	3	0	0
T183	0	2	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	155	0	0
T8	1170	5	0	0
T26	1841	0	0	0
T27	1207	5	0	0
T28	1195	7	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0
T43	1431	0	0	0
T44	1925	0	0	0
T60	0	6	0	0
T62	0	2	0	0
T84	0	4	0	0
T86	0	2	0	0
T178	0	1	0	0
T182	0	3	0	0
T183	0	2	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	155	0	0
T8	1170	5	0	0
T26	1841	0	0	0
T27	1207	5	0	0
T28	1195	7	0	0
T29	1789	0	0	0
T30	1601	0	0	0
T31	2442	0	0	0
T32	1545	0	0	0
T43	1431	0	0	0
T44	1925	0	0	0
T60	0	6	0	0
T62	0	2	0	0
T84	0	4	0	0
T86	0	2	0	0
T178	0	1	0	0
T182	0	3	0	0
T183	0	2	0	0