Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47049	0	0
CgEnOn_A	2147483647	38203	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47049	0	0
T3	0	5	0	0
T6	307141	3	0	0
T7	19139	3	0	0
T8	21645	63	0	0
T16	0	5	0	0
T26	79514	3	0	0
T27	102126	33	0	0
T28	41949	64	0	0
T29	19248	3	0	0
T30	19676	3	0	0
T31	25155	8	0	0
T32	15896	3	0	0
T41	0	3	0	0
T42	0	5	0	0
T43	24373	0	0	0
T44	121963	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T60	0	25	0	0
T62	0	5	0	0
T84	0	20	0	0
T86	0	10	0	0
T182	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38203	0	0
T1	0	127	0	0
T2	0	84	0	0
T3	0	5	0	0
T8	21645	60	0	0
T16	0	4	0	0
T21	0	3	0	0
T24	0	3	0	0
T25	0	3	0	0
T26	79514	0	0	0
T27	102126	30	0	0
T28	41949	61	0	0
T29	19248	0	0	0
T30	19676	0	0	0
T31	25155	5	0	0
T32	15896	0	0	0
T41	0	3	0	0
T42	0	5	0	0
T43	30841	0	0	0
T44	154638	0	0	0
T45	0	4	0	0
T46	0	4	0	0
T60	0	25	0	0
T62	0	5	0	0
T84	0	20	0	0
T86	0	10	0	0
T182	0	15	0	0
T183	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	199268693	157	0	0
CgEnOn_A	199268693	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199268693	157	0	0
T3	0	1	0	0
T8	997	7	0	0
T16	0	1	0	0
T26	3761	0	0	0
T27	4446	3	0	0
T28	2042	7	0	0
T29	857	0	0	0
T30	914	0	0	0
T31	1160	0	0	0
T32	699	0	0	0
T43	1450	0	0	0
T44	7572	0	0	0
T60	0	5	0	0
T62	0	1	0	0
T84	0	4	0	0
T86	0	2	0	0
T182	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199268693	157	0	0
T3	0	1	0	0
T8	997	7	0	0
T16	0	1	0	0
T26	3761	0	0	0
T27	4446	3	0	0
T28	2042	7	0	0
T29	857	0	0	0
T30	914	0	0	0
T31	1160	0	0	0
T32	699	0	0	0
T43	1450	0	0	0
T44	7572	0	0	0
T60	0	5	0	0
T62	0	1	0	0
T84	0	4	0	0
T86	0	2	0	0
T182	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99633745	157	0	0
CgEnOn_A	99633745	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99633745	157	0	0
T3	0	1	0	0
T8	499	7	0	0
T16	0	1	0	0
T26	1881	0	0	0
T27	2223	3	0	0
T28	1021	7	0	0
T29	429	0	0	0
T30	457	0	0	0
T31	580	0	0	0
T32	350	0	0	0
T43	725	0	0	0
T44	3785	0	0	0
T60	0	5	0	0
T62	0	1	0	0
T84	0	4	0	0
T86	0	2	0	0
T182	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99633745	157	0	0
T3	0	1	0	0
T8	499	7	0	0
T16	0	1	0	0
T26	1881	0	0	0
T27	2223	3	0	0
T28	1021	7	0	0
T29	429	0	0	0
T30	457	0	0	0
T31	580	0	0	0
T32	350	0	0	0
T43	725	0	0	0
T44	3785	0	0	0
T60	0	5	0	0
T62	0	1	0	0
T84	0	4	0	0
T86	0	2	0	0
T182	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	399449316	157	0	0
CgEnOn_A	399449316	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399449316	157	0	0
T3	0	1	0	0
T8	2019	7	0	0
T16	0	1	0	0
T26	7367	0	0	0
T27	8971	3	0	0
T28	4205	7	0	0
T29	1808	0	0	0
T30	1831	0	0	0
T31	2345	0	0	0
T32	1498	0	0	0
T43	2862	0	0	0
T44	14212	0	0	0
T60	0	5	0	0
T62	0	1	0	0
T84	0	4	0	0
T86	0	2	0	0
T182	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399449316	146	0	0
T3	0	1	0	0
T8	2019	7	0	0
T26	7367	0	0	0
T27	8971	3	0	0
T28	4205	7	0	0
T29	1808	0	0	0
T30	1831	0	0	0
T31	2345	0	0	0
T32	1498	0	0	0
T43	2862	0	0	0
T44	14212	0	0	0
T60	0	5	0	0
T62	0	1	0	0
T84	0	4	0	0
T86	0	2	0	0
T182	0	3	0	0
T183	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	427231722	148	0	0
CgEnOn_A	427231722	148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427231722	148	0	0
T8	2097	4	0	0
T26	7675	0	0	0
T27	10288	6	0	0
T28	3888	5	0	0
T29	1883	0	0	0
T30	1907	0	0	0
T31	2442	0	0	0
T32	1559	0	0	0
T43	2981	0	0	0
T44	14804	0	0	0
T60	0	3	0	0
T62	0	1	0	0
T84	0	2	0	0
T86	0	2	0	0
T178	0	2	0	0
T182	0	3	0	0
T183	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427231722	148	0	0
T8	2097	4	0	0
T26	7675	0	0	0
T27	10288	6	0	0
T28	3888	5	0	0
T29	1883	0	0	0
T30	1907	0	0	0
T31	2442	0	0	0
T32	1559	0	0	0
T43	2981	0	0	0
T44	14804	0	0	0
T60	0	3	0	0
T62	0	1	0	0
T84	0	2	0	0
T86	0	2	0	0
T178	0	2	0	0
T182	0	3	0	0
T183	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99633745	157	0	0
CgEnOn_A	99633745	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99633745	157	0	0
T3	0	1	0	0
T8	499	7	0	0
T16	0	1	0	0
T26	1881	0	0	0
T27	2223	3	0	0
T28	1021	7	0	0
T29	429	0	0	0
T30	457	0	0	0
T31	580	0	0	0
T32	350	0	0	0
T43	725	0	0	0
T44	3785	0	0	0
T60	0	5	0	0
T62	0	1	0	0
T84	0	4	0	0
T86	0	2	0	0
T182	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99633745	157	0	0
T3	0	1	0	0
T8	499	7	0	0
T16	0	1	0	0
T26	1881	0	0	0
T27	2223	3	0	0
T28	1021	7	0	0
T29	429	0	0	0
T30	457	0	0	0
T31	580	0	0	0
T32	350	0	0	0
T43	725	0	0	0
T44	3785	0	0	0
T60	0	5	0	0
T62	0	1	0	0
T84	0	4	0	0
T86	0	2	0	0
T182	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	427231722	148	0	0
CgEnOn_A	427231722	148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427231722	148	0	0
T8	2097	4	0	0
T26	7675	0	0	0
T27	10288	6	0	0
T28	3888	5	0	0
T29	1883	0	0	0
T30	1907	0	0	0
T31	2442	0	0	0
T32	1559	0	0	0
T43	2981	0	0	0
T44	14804	0	0	0
T60	0	3	0	0
T62	0	1	0	0
T84	0	2	0	0
T86	0	2	0	0
T178	0	2	0	0
T182	0	3	0	0
T183	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427231722	148	0	0
T8	2097	4	0	0
T26	7675	0	0	0
T27	10288	6	0	0
T28	3888	5	0	0
T29	1883	0	0	0
T30	1907	0	0	0
T31	2442	0	0	0
T32	1559	0	0	0
T43	2981	0	0	0
T44	14804	0	0	0
T60	0	3	0	0
T62	0	1	0	0
T84	0	2	0	0
T86	0	2	0	0
T178	0	2	0	0
T182	0	3	0	0
T183	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99633745	157	0	0
CgEnOn_A	99633745	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99633745	157	0	0
T3	0	1	0	0
T8	499	7	0	0
T16	0	1	0	0
T26	1881	0	0	0
T27	2223	3	0	0
T28	1021	7	0	0
T29	429	0	0	0
T30	457	0	0	0
T31	580	0	0	0
T32	350	0	0	0
T43	725	0	0	0
T44	3785	0	0	0
T60	0	5	0	0
T62	0	1	0	0
T84	0	4	0	0
T86	0	2	0	0
T182	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99633745	157	0	0
T3	0	1	0	0
T8	499	7	0	0
T16	0	1	0	0
T26	1881	0	0	0
T27	2223	3	0	0
T28	1021	7	0	0
T29	429	0	0	0
T30	457	0	0	0
T31	580	0	0	0
T32	350	0	0	0
T43	725	0	0	0
T44	3785	0	0	0
T60	0	5	0	0
T62	0	1	0	0
T84	0	4	0	0
T86	0	2	0	0
T182	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	199268693	7591	0	0
CgEnOn_A	199268693	5388	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199268693	7591	0	0
T6	64382	1	0	0
T7	4452	1	0	0
T8	997	8	0	0
T26	3761	1	0	0
T27	4446	4	0	0
T28	2042	8	0	0
T29	857	1	0	0
T30	914	1	0	0
T31	1160	1	0	0
T32	699	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199268693	5388	0	0
T1	0	35	0	0
T2	0	30	0	0
T8	997	7	0	0
T21	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	3761	0	0	0
T27	4446	3	0	0
T28	2042	7	0	0
T29	857	0	0	0
T30	914	0	0	0
T31	1160	0	0	0
T32	699	0	0	0
T43	1450	0	0	0
T44	7572	0	0	0
T45	0	1	0	0
T46	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99633745	7550	0	0
CgEnOn_A	99633745	5347	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99633745	7550	0	0
T6	32191	1	0	0
T7	2226	1	0	0
T8	499	8	0	0
T26	1881	1	0	0
T27	2223	4	0	0
T28	1021	8	0	0
T29	429	1	0	0
T30	457	1	0	0
T31	580	1	0	0
T32	350	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99633745	5347	0	0
T1	0	34	0	0
T2	0	26	0	0
T8	499	7	0	0
T21	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	1881	0	0	0
T27	2223	3	0	0
T28	1021	7	0	0
T29	429	0	0	0
T30	457	0	0	0
T31	580	0	0	0
T32	350	0	0	0
T43	725	0	0	0
T44	3785	0	0	0
T45	0	1	0	0
T46	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	399449316	7647	0	0
CgEnOn_A	399449316	5433	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399449316	7647	0	0
T6	128856	1	0	0
T7	8308	1	0	0
T8	2019	8	0	0
T26	7367	1	0	0
T27	8971	4	0	0
T28	4205	8	0	0
T29	1808	1	0	0
T30	1831	1	0	0
T31	2345	1	0	0
T32	1498	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399449316	5433	0	0
T1	0	35	0	0
T2	0	28	0	0
T8	2019	7	0	0
T21	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	7367	0	0	0
T27	8971	3	0	0
T28	4205	7	0	0
T29	1808	0	0	0
T30	1831	0	0	0
T31	2345	0	0	0
T32	1498	0	0	0
T43	2862	0	0	0
T44	14212	0	0	0
T45	0	1	0	0
T46	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	205104417	7646	0	0
CgEnOn_A	205104417	5431	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205104417	7646	0	0
T6	81712	1	0	0
T7	4153	1	0	0
T8	1035	6	0	0
T26	3684	1	0	0
T27	4672	6	0	0
T28	2043	8	0	0
T29	904	1	0	0
T30	916	1	0	0
T31	1173	1	0	0
T32	748	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205104417	5431	0	0
T1	0	33	0	0
T2	0	29	0	0
T8	1035	5	0	0
T21	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	3684	0	0	0
T27	4672	5	0	0
T28	2043	7	0	0
T29	904	0	0	0
T30	916	0	0	0
T31	1173	0	0	0
T32	748	0	0	0
T43	1431	0	0	0
T44	7106	0	0	0
T45	0	1	0	0
T46	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Covered	T31,T41,T42
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	427231722	3841	0	0
CgEnOn_A	427231722	3841	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427231722	3841	0	0
T1	0	23	0	0
T8	2097	4	0	0
T20	0	5	0	0
T26	7675	0	0	0
T27	10288	6	0	0
T28	3888	5	0	0
T29	1883	0	0	0
T30	1907	0	0	0
T31	2442	5	0	0
T32	1559	0	0	0
T41	0	3	0	0
T42	0	5	0	0
T43	2981	0	0	0
T44	14804	0	0	0
T45	0	1	0	0
T46	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427231722	3841	0	0
T1	0	23	0	0
T8	2097	4	0	0
T20	0	5	0	0
T26	7675	0	0	0
T27	10288	6	0	0
T28	3888	5	0	0
T29	1883	0	0	0
T30	1907	0	0	0
T31	2442	5	0	0
T32	1559	0	0	0
T41	0	3	0	0
T42	0	5	0	0
T43	2981	0	0	0
T44	14804	0	0	0
T45	0	1	0	0
T46	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Covered	T29,T31,T41
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	427231722	3914	0	0
CgEnOn_A	427231722	3914	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427231722	3914	0	0
T1	0	29	0	0
T8	2097	4	0	0
T26	7675	0	0	0
T27	10288	6	0	0
T28	3888	5	0	0
T29	1883	1	0	0
T30	1907	0	0	0
T31	2442	5	0	0
T32	1559	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	2981	0	0	0
T44	14804	0	0	0
T45	0	1	0	0
T46	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427231722	3914	0	0
T1	0	29	0	0
T8	2097	4	0	0
T26	7675	0	0	0
T27	10288	6	0	0
T28	3888	5	0	0
T29	1883	1	0	0
T30	1907	0	0	0
T31	2442	5	0	0
T32	1559	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	2981	0	0	0
T44	14804	0	0	0
T45	0	1	0	0
T46	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Covered	T29,T31,T41
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	427231722	3862	0	0
CgEnOn_A	427231722	3862	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427231722	3862	0	0
T1	0	24	0	0
T8	2097	4	0	0
T26	7675	0	0	0
T27	10288	6	0	0
T28	3888	5	0	0
T29	1883	1	0	0
T30	1907	0	0	0
T31	2442	3	0	0
T32	1559	0	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	2981	0	0	0
T44	14804	0	0	0
T45	0	1	0	0
T46	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427231722	3862	0	0
T1	0	24	0	0
T8	2097	4	0	0
T26	7675	0	0	0
T27	10288	6	0	0
T28	3888	5	0	0
T29	1883	1	0	0
T30	1907	0	0	0
T31	2442	3	0	0
T32	1559	0	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	2981	0	0	0
T44	14804	0	0	0
T45	0	1	0	0
T46	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T28
1	0	Covered	T29,T31,T41
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	427231722	3917	0	0
CgEnOn_A	427231722	3917	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427231722	3917	0	0
T1	0	25	0	0
T8	2097	4	0	0
T26	7675	0	0	0
T27	10288	6	0	0
T28	3888	5	0	0
T29	1883	1	0	0
T30	1907	0	0	0
T31	2442	3	0	0
T32	1559	0	0	0
T41	0	3	0	0
T42	0	3	0	0
T43	2981	0	0	0
T44	14804	0	0	0
T45	0	1	0	0
T46	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427231722	3917	0	0
T1	0	25	0	0
T8	2097	4	0	0
T26	7675	0	0	0
T27	10288	6	0	0
T28	3888	5	0	0
T29	1883	1	0	0
T30	1907	0	0	0
T31	2442	3	0	0
T32	1559	0	0	0
T41	0	3	0	0
T42	0	3	0	0
T43	2981	0	0	0
T44	14804	0	0	0
T45	0	1	0	0
T46	0	1	0	0