Module Definition
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Module : clkmgr_clk_status
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_main_status 100.00 100.00 100.00
tb.dut.u_io_status 100.00 100.00 100.00
tb.dut.u_usb_status 100.00 100.00 100.00



Module Instance : tb.dut.u_main_status

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_en_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_status

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_en_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_status

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_en_sync 100.00 100.00 100.00

Line Coverage for Module : clkmgr_clk_status
Line No.TotalCoveredPercent
TOTAL1313100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3611100.00
ALWAYS3955100.00
ALWAYS4966100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
36 1 1
39 1 1
40 1 1
41 1 1
43 1 1
44 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
MISSING_ELSE


Branch Coverage for Module : clkmgr_clk_status
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 39 2 2 100.00
IF 49 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 39 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 49 if ((!rst_ni)) -2-: 51 if ((&en_q)) -3-: 53 if ((&dis_q))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T6,T7,T8
0 0 1 Covered T6,T7,T8
0 0 0 Covered T6,T7,T8

Line Coverage for Instance : tb.dut.u_main_status
Line No.TotalCoveredPercent
TOTAL1313100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3611100.00
ALWAYS3955100.00
ALWAYS4966100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
36 1 1
39 1 1
40 1 1
41 1 1
43 1 1
44 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_main_status
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 39 2 2 100.00
IF 49 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 39 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 49 if ((!rst_ni)) -2-: 51 if ((&en_q)) -3-: 53 if ((&dis_q))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T6,T7,T8
0 0 1 Covered T6,T7,T8
0 0 0 Covered T6,T7,T8

Line Coverage for Instance : tb.dut.u_io_status
Line No.TotalCoveredPercent
TOTAL1313100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3611100.00
ALWAYS3955100.00
ALWAYS4966100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
36 1 1
39 1 1
40 1 1
41 1 1
43 1 1
44 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_io_status
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 39 2 2 100.00
IF 49 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 39 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 49 if ((!rst_ni)) -2-: 51 if ((&en_q)) -3-: 53 if ((&dis_q))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T6,T7,T8
0 0 1 Covered T6,T7,T8
0 0 0 Covered T6,T7,T8

Line Coverage for Instance : tb.dut.u_usb_status
Line No.TotalCoveredPercent
TOTAL1313100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3611100.00
ALWAYS3955100.00
ALWAYS4966100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
36 1 1
39 1 1
40 1 1
41 1 1
43 1 1
44 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_usb_status
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 39 2 2 100.00
IF 49 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 39 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 49 if ((!rst_ni)) -2-: 51 if ((&en_q)) -3-: 53 if ((&dis_q))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T6,T7,T8
0 0 1 Covered T6,T7,T8
0 0 0 Covered T6,T7,T8

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%