Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	667678	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3853706

1

T1

388

T6

24

T4

380

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1104935	1			T1	207		T6	42		T4	408
values[0x0]	1568195	1			T1	323		T6	22		T4	182
values[0x1]	1848254	1			T1	320		T6	17		T4	209

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	364828	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4156556

1

T1

489

T6

35

T4

493

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17098	1			T1	10		T5	2		T17	1
valid_sources[0x01]	18116	1			T1	2		T2	89		T3	3
valid_sources[0x02]	17603	1			T1	1		T4	3		T5	1
valid_sources[0x03]	16699	1			T1	1		T4	5		T5	3
valid_sources[0x04]	16968	1			T1	4		T5	1		T2	209
valid_sources[0x05]	18454	1			T1	11		T4	2		T2	418
valid_sources[0x06]	19051	1			T5	1		T2	220		T21	3
valid_sources[0x07]	16815	1			T1	3		T5	3		T2	411
valid_sources[0x08]	18295	1			T1	3		T6	1		T4	1
valid_sources[0x09]	18403	1			T1	3		T4	2		T17	1
valid_sources[0x0a]	17198	1			T1	4		T4	2		T5	1
valid_sources[0x0b]	19523	1			T1	2		T17	1		T2	317
valid_sources[0x0c]	17238	1			T1	11		T5	4		T2	84
valid_sources[0x0d]	18185	1			T1	2		T6	1		T4	6
valid_sources[0x0e]	17838	1			T1	1		T4	6		T2	32
valid_sources[0x0f]	18065	1			T1	1		T4	3		T5	1
valid_sources[0x10]	17908	1			T1	1		T4	1		T5	1
valid_sources[0x11]	16674	1			T1	6		T6	1		T4	2
valid_sources[0x12]	17313	1			T1	2		T4	3		T2	40
valid_sources[0x13]	17522	1			T1	7		T4	4		T2	31
valid_sources[0x14]	16405	1			T1	2		T4	3		T17	2
valid_sources[0x15]	18577	1			T4	2		T2	243		T21	8
valid_sources[0x16]	18075	1			T1	6		T2	204		T21	1
valid_sources[0x17]	17660	1			T1	10		T6	1		T4	3
valid_sources[0x18]	17716	1			T1	4		T5	2		T2	42
valid_sources[0x19]	16562	1			T1	2		T4	4		T5	1
valid_sources[0x1a]	16870	1			T6	1		T4	5		T2	651
valid_sources[0x1b]	16890	1			T1	4		T2	392		T21	5
valid_sources[0x1c]	17522	1			T1	3		T5	1		T17	2
valid_sources[0x1d]	17396	1			T1	4		T2	38		T21	3
valid_sources[0x1e]	15889	1			T1	2		T5	1		T2	255
valid_sources[0x1f]	18864	1			T1	8		T4	6		T2	202
valid_sources[0x20]	16172	1			T1	8		T6	1		T4	3
valid_sources[0x21]	17271	1			T4	3		T17	1		T2	47
valid_sources[0x22]	17777	1			T2	209		T21	3		T10	452
valid_sources[0x23]	17536	1			T1	4		T2	316		T21	2
valid_sources[0x24]	17967	1			T1	7		T4	4		T2	122
valid_sources[0x25]	17461	1			T1	3		T2	344		T3	1
valid_sources[0x26]	15720	1			T1	1		T5	2		T2	7
valid_sources[0x27]	16310	1			T1	7		T4	7		T17	1
valid_sources[0x28]	18661	1			T1	1		T4	6		T2	310
valid_sources[0x29]	18072	1			T1	6		T6	1		T4	3
valid_sources[0x2a]	17240	1			T1	1		T2	148		T21	9
valid_sources[0x2b]	19224	1			T1	5		T6	1		T2	138
valid_sources[0x2c]	16809	1			T1	4		T6	2		T4	5
valid_sources[0x2d]	18302	1			T1	2		T4	5		T2	25
valid_sources[0x2e]	16987	1			T1	3		T5	1		T2	256
valid_sources[0x2f]	16940	1			T1	1		T4	1		T5	1
valid_sources[0x30]	18236	1			T1	1		T4	5		T2	451
valid_sources[0x31]	17851	1			T1	3		T4	6		T2	338
valid_sources[0x32]	18017	1			T1	3		T4	9		T2	301
valid_sources[0x33]	19060	1			T1	3		T6	1		T4	6
valid_sources[0x34]	16212	1			T1	3		T6	1		T17	1
valid_sources[0x35]	17271	1			T1	4		T4	3		T5	3
valid_sources[0x36]	18265	1			T1	3		T2	317		T21	1
valid_sources[0x37]	16441	1			T1	2		T5	3		T2	71
valid_sources[0x38]	16509	1			T4	14		T5	2		T2	426
valid_sources[0x39]	16674	1			T1	1		T4	2		T2	222
valid_sources[0x3a]	17633	1			T1	2		T4	4		T5	1
valid_sources[0x3b]	18895	1			T1	5		T5	2		T2	171
valid_sources[0x3c]	17011	1			T1	1		T4	3		T2	97
valid_sources[0x3d]	16266	1			T1	1		T6	1		T4	1
valid_sources[0x3e]	16571	1			T1	2		T5	3		T2	12
valid_sources[0x3f]	15526	1			T1	2		T6	2		T2	8
valid_sources[0x40]	18650	1			T1	3		T6	1		T17	1
valid_sources[0x41]	17828	1			T1	7		T4	6		T17	2
valid_sources[0x42]	17781	1			T1	4		T4	8		T5	1
valid_sources[0x43]	18972	1			T1	5		T4	3		T2	350
valid_sources[0x44]	19121	1			T1	5		T6	1		T5	8
valid_sources[0x45]	16325	1			T1	2		T6	2		T4	6
valid_sources[0x46]	17738	1			T1	5		T4	10		T5	1
valid_sources[0x47]	18061	1			T1	9		T6	1		T4	5
valid_sources[0x48]	17296	1			T1	5		T5	1		T2	19
valid_sources[0x49]	19348	1			T1	2		T4	6		T2	135
valid_sources[0x4a]	16603	1			T1	16		T17	1		T2	239
valid_sources[0x4b]	17438	1			T1	3		T6	1		T4	21
valid_sources[0x4c]	17606	1			T1	2		T6	1		T2	85
valid_sources[0x4d]	17784	1			T1	1		T4	5		T2	187
valid_sources[0x4e]	17266	1			T1	5		T6	1		T4	1
valid_sources[0x4f]	18368	1			T1	9		T4	6		T2	324
valid_sources[0x50]	17724	1			T1	2		T4	2		T5	3
valid_sources[0x51]	17724	1			T1	5		T6	2		T4	6
valid_sources[0x52]	17662	1			T1	2		T4	1		T2	224
valid_sources[0x53]	17835	1			T1	1		T6	1		T4	3
valid_sources[0x54]	16868	1			T1	3		T6	1		T5	2
valid_sources[0x55]	16631	1			T1	6		T4	1		T5	1
valid_sources[0x56]	17126	1			T1	3		T2	259		T3	3
valid_sources[0x57]	18195	1			T1	5		T4	4		T5	1
valid_sources[0x58]	18590	1			T1	1		T6	1		T4	21
valid_sources[0x59]	16680	1			T1	1		T4	6		T2	64
valid_sources[0x5a]	17789	1			T4	1		T2	103		T21	1
valid_sources[0x5b]	18903	1			T1	1		T5	2		T2	301
valid_sources[0x5c]	17362	1			T1	3		T6	1		T4	9
valid_sources[0x5d]	16456	1			T1	11		T4	2		T17	1
valid_sources[0x5e]	18950	1			T1	5		T6	1		T2	17
valid_sources[0x5f]	17892	1			T1	4		T4	9		T2	406
valid_sources[0x60]	17367	1			T1	5		T6	2		T4	7
valid_sources[0x61]	16886	1			T1	2		T5	1		T17	1
valid_sources[0x62]	18602	1			T1	3		T4	12		T5	2
valid_sources[0x63]	16886	1			T1	5		T4	4		T2	108
valid_sources[0x64]	16818	1			T1	3		T2	122		T19	46
valid_sources[0x65]	17465	1			T1	3		T5	2		T2	21
valid_sources[0x66]	18029	1			T1	3		T4	1		T2	58
valid_sources[0x67]	18290	1			T1	4		T4	2		T5	1
valid_sources[0x68]	18174	1			T1	2		T4	16		T2	232
valid_sources[0x69]	18358	1			T1	1		T4	7		T17	2
valid_sources[0x6a]	18454	1			T1	3		T6	1		T4	2
valid_sources[0x6b]	16431	1			T1	1		T4	5		T5	2
valid_sources[0x6c]	18501	1			T1	5		T6	1		T4	3
valid_sources[0x6d]	18024	1			T1	3		T6	1		T4	7
valid_sources[0x6e]	17754	1			T1	7		T6	1		T4	5
valid_sources[0x6f]	17290	1			T1	2		T2	52		T21	4
valid_sources[0x70]	17625	1			T1	3		T4	6		T2	128
valid_sources[0x71]	18191	1			T1	6		T2	533		T21	1
valid_sources[0x72]	17085	1			T4	2		T2	37		T21	3
valid_sources[0x73]	17132	1			T1	2		T2	161		T21	8
valid_sources[0x74]	18410	1			T4	6		T5	3		T2	255
valid_sources[0x75]	17596	1			T1	4		T6	1		T4	1
valid_sources[0x76]	17139	1			T1	2		T4	4		T5	2
valid_sources[0x77]	17891	1			T1	2		T4	1		T5	1
valid_sources[0x78]	17581	1			T1	2		T4	1		T2	22
valid_sources[0x79]	18279	1			T1	1		T4	2		T2	327
valid_sources[0x7a]	16839	1			T1	9		T4	3		T5	5
valid_sources[0x7b]	17466	1			T1	3		T2	447		T21	1
valid_sources[0x7c]	17137	1			T5	3		T2	127		T21	2
valid_sources[0x7d]	15640	1			T1	7		T4	1		T5	1
valid_sources[0x7e]	16014	1			T1	5		T2	117		T28	9
valid_sources[0x7f]	18995	1			T1	3		T4	12		T5	3
valid_sources[0x80]	18141	1			T1	2		T6	1		T4	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

970198

1

T1

89

T6

19

T4

211

values[0x0]

all_enables

biggest_size

1467488

1

T1

195

T6

4

T4

109

values[0x1]

all_enables

biggest_size

1416020

1

T1

104

T6

1

T4

60