Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_peri_cg_wrap::peri_cg

Group : clkmgr_env_pkg::clkmgr_peri_cg_wrap::peri_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
PeriDiv2	100.00	1	100	1	64	64
PeriDiv4	100.00	1	100	1	64	64
PeriIo	100.00	1	100	1	64	64
PeriUsb	100.00	1	100	1	64	64

---

Group Instance : PeriDiv2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriDiv2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriDiv2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriDiv2

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

---

Group Instance : PeriDiv4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriDiv4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriDiv4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriDiv4

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

---

Group Instance : PeriIo

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriIo

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriIo

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriIo

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

---

Group Instance : PeriUsb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance PeriUsb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group Instance PeriUsb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_enable_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance PeriUsb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
peri_cross	6	0	6	100.00	100	1	1	0

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296991

1

T1

47

T6

37

T4

36

auto[1]

217921559

1

T1

116279

T6

3009

T4

12381

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8508

1

T1

14

T6

2

T4

36

auto[1]

218210042

1

T1

116312

T6

3044

T4

12381

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127649715

1

T1

113798

T6

3025

T4

12398

auto[1]

90568835

1

T1

2528

T6

21

T4

19

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

5224

1

T1

8

T4

34

T5

10

auto[0]

auto[0]

auto[1]

1564

1

T1

6

T6

2

T4

2

auto[0]

auto[1]

auto[0]

223590

1

T1

27

T6

35

T2

266

auto[0]

auto[1]

auto[1]

66613

1

T1

6

T2

239

T20

170

auto[1]

auto[1]

auto[0]

127419181

1

T1

113763

T6

2990

T4

12364

auto[1]

auto[1]

auto[1]

90500658

1

T1

2516

T6

19

T4

17

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

151650

1

T1

33

T6

19

T4

36

auto[1]

108955639

1

T1

58130

T6

1504

T4

6173

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7661

1

T1

14

T6

2

T4

36

auto[1]

109099628

1

T1

58149

T6

1521

T4

6173

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63822874

1

T1

56898

T6

1513

T4

6200

auto[1]

45284415

1

T1

1265

T6

10

T4

9

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

5224

1

T1

8

T4

34

T5

10

auto[0]

auto[0]

auto[1]

1564

1

T1

6

T6

2

T4

2

auto[0]

auto[1]

auto[0]

112076

1

T1

13

T6

17

T2

144

auto[0]

auto[1]

auto[1]

32786

1

T1

6

T2

100

T20

111

auto[1]

auto[1]

auto[0]

63704701

1

T1

56877

T6

1496

T4

6166

auto[1]

auto[1]

auto[1]

45250065

1

T1

1253

T6

8

T4

7

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

576903

1

T1

79

T6

71

T4

36

auto[1]

435270461

1

T1

232502

T6

6021

T4

24792

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10221

1

T1

14

T6

2

T4

36

auto[1]

435837143

1

T1

232567

T6

6090

T4

24792

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

254709741

1

T1

227526

T6

6051

T4

24791

auto[1]

181137623

1

T1

5055

T6

41

T4

37

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

5224

1

T1

8

T4

34

T5

10

auto[0]

auto[0]

auto[1]

1564

1

T1

6

T6

2

T4

2

auto[0]

auto[1]

auto[0]

436580

1

T1

47

T6

69

T2

595

auto[0]

auto[1]

auto[1]

133535

1

T1

18

T2

401

T20

363

auto[1]

auto[1]

auto[0]

254264504

1

T1

227471

T6

5982

T4

24757

auto[1]

auto[1]

auto[1]

181002524

1

T1

5031

T6

39

T4

35

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded

Summary for Variable csr_enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289754

1

T1

48

T6

36

T4

36

auto[1]

223794817

1

T1

133530

T6

3010

T4

12378

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8223

1

T1

14

T6

2

T4

36

auto[1]

224076348

1

T1

133564

T6

3044

T4

12378

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

131241005

1

T1

131050

T6

3026

T4

12396

auto[1]

92843566

1

T1

2528

T6

20

T4

18

---

Summary for Cross peri_cross

Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for peri_cross

Bins

csr_enable_cp

ip_clk_en_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

5216

1

T1

8

T4

34

T5

10

auto[0]

auto[0]

auto[1]

1572

1

T1

6

T6

2

T4

2

auto[0]

auto[1]

auto[0]

217371

1

T1

25

T6

34

T2

300

auto[0]

auto[1]

auto[1]

65595

1

T1

9

T2

221

T20

265

auto[1]

auto[1]

auto[0]

131016983

1

T1

131017

T6

2992

T4

12362

auto[1]

auto[1]

auto[1]

92776399

1

T1

2513

T6

18

T4

16

User Defined Cross Bins for peri_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_enable_off	0	Excluded