Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T36,T37,T38
1	1	Covered	T1,T6,T4

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	990472707	14227	0	0
GateOpen_A	990472707	20744	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990472707	14227	0	0
T1	542725	20	0	0
T2	2436177	105	0	0
T4	267811	0	0	0
T5	64447	0	0	0
T6	14160	4	0	0
T10	0	252	0	0
T11	0	290	0	0
T17	13897	0	0	0
T18	9068	0	0	0
T19	7592	0	0	0
T20	15921	12	0	0
T21	169638	0	0	0
T36	0	3	0	0
T37	0	9	0	0
T109	0	3	0	0
T152	0	27	0	0
T160	0	24	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	990472707	20744	0	0
T1	542725	36	0	0
T2	2436177	117	0	0
T4	267811	68	0	0
T5	64447	20	0	0
T6	14160	4	0	0
T17	13897	0	0	0
T18	9068	0	0	0
T19	7592	4	0	0
T20	15921	12	0	0
T21	169638	60	0	0
T25	0	4	0	0
T27	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T36,T37,T38
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	109106007	3372	0	0
GateOpen_A	109106007	4999	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109106007	3372	0	0
T1	58294	5	0	0
T2	439125	24	0	0
T4	21591	0	0	0
T5	5139	0	0	0
T6	1551	1	0	0
T10	0	65	0	0
T11	0	68	0	0
T17	1608	0	0	0
T18	1039	0	0	0
T19	877	0	0	0
T20	1751	3	0	0
T21	11718	0	0	0
T36	0	1	0	0
T37	0	4	0	0
T152	0	6	0	0
T160	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109106007	4999	0	0
T1	58294	9	0	0
T2	439125	27	0	0
T4	21591	17	0	0
T5	5139	5	0	0
T6	1551	1	0	0
T17	1608	0	0	0
T18	1039	0	0	0
T19	877	1	0	0
T20	1751	3	0	0
T21	11718	15	0	0
T25	0	1	0	0
T27	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T36,T37,T38
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	218212992	3624	0	0
GateOpen_A	218212992	5251	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218212992	3624	0	0
T1	116590	5	0	0
T2	878261	27	0	0
T4	43178	0	0	0
T5	10278	0	0	0
T6	3102	1	0	0
T10	0	63	0	0
T11	0	72	0	0
T17	3218	0	0	0
T18	2077	0	0	0
T19	1756	0	0	0
T20	3502	3	0	0
T21	23431	0	0	0
T36	0	1	0	0
T109	0	1	0	0
T152	0	7	0	0
T160	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218212992	5251	0	0
T1	116590	9	0	0
T2	878261	30	0	0
T4	43178	17	0	0
T5	10278	5	0	0
T6	3102	1	0	0
T17	3218	0	0	0
T18	2077	0	0	0
T19	1756	1	0	0
T20	3502	3	0	0
T21	23431	15	0	0
T25	0	1	0	0
T27	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T36,T37,T38
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	437983902	3600	0	0
GateOpen_A	437983902	5232	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437983902	3600	0	0
T1	233703	5	0	0
T2	175898	25	0	0
T4	135359	0	0	0
T5	32686	0	0	0
T6	6338	1	0	0
T10	0	61	0	0
T11	0	78	0	0
T17	6047	0	0	0
T18	3968	0	0	0
T19	3306	0	0	0
T20	7112	3	0	0
T21	89658	0	0	0
T36	0	1	0	0
T109	0	1	0	0
T152	0	7	0	0
T160	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437983902	5232	0	0
T1	233703	9	0	0
T2	175898	28	0	0
T4	135359	17	0	0
T5	32686	5	0	0
T6	6338	1	0	0
T17	6047	0	0	0
T18	3968	0	0	0
T19	3306	1	0	0
T20	7112	3	0	0
T21	89658	15	0	0
T25	0	1	0	0
T27	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T37,T38,T39
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	225169806	3631	0	0
GateOpen_A	225169806	5262	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225169806	3631	0	0
T1	134138	5	0	0
T2	942893	29	0	0
T4	67683	0	0	0
T5	16344	0	0	0
T6	3169	1	0	0
T10	0	63	0	0
T11	0	72	0	0
T17	3024	0	0	0
T18	1984	0	0	0
T19	1653	0	0	0
T20	3556	3	0	0
T21	44831	0	0	0
T37	0	5	0	0
T109	0	1	0	0
T152	0	7	0	0
T160	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225169806	5262	0	0
T1	134138	9	0	0
T2	942893	32	0	0
T4	67683	17	0	0
T5	16344	5	0	0
T6	3169	1	0	0
T17	3024	0	0	0
T18	1984	0	0	0
T19	1653	1	0	0
T20	3556	3	0	0
T21	44831	15	0	0
T25	0	1	0	0
T27	0	1	0	0