Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	861246425	81362	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	861246425	81362	0	0
T1	713620	138	0	0
T2	1007985	281	0	0
T3	0	79	0	0
T4	176250	0	0	0
T5	160035	0	0	0
T6	8245	0	0	0
T10	0	787	0	0
T11	0	1264	0	0
T12	0	298	0	0
T13	0	1032	0	0
T14	0	87	0	0
T15	0	713	0	0
T16	0	425	0	0
T17	7870	0	0	0
T18	8880	0	0	0
T19	8605	0	0	0
T20	3335	0	0	0
T21	224155	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172249285	11801	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172249285	11801	0	0
T1	142724	20	0	0
T2	201597	38	0	0
T3	0	12	0	0
T4	35250	0	0	0
T5	32007	0	0	0
T6	1649	0	0	0
T10	0	129	0	0
T11	0	187	0	0
T12	0	39	0	0
T13	0	166	0	0
T14	0	11	0	0
T15	0	95	0	0
T16	0	56	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172249285	16343	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172249285	16343	0	0
T1	142724	28	0	0
T2	201597	57	0	0
T3	0	16	0	0
T4	35250	0	0	0
T5	32007	0	0	0
T6	1649	0	0	0
T10	0	158	0	0
T11	0	252	0	0
T12	0	60	0	0
T13	0	211	0	0
T14	0	17	0	0
T15	0	143	0	0
T16	0	86	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172249285	25107	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172249285	25107	0	0
T1	142724	43	0	0
T2	201597	92	0	0
T3	0	23	0	0
T4	35250	0	0	0
T5	32007	0	0	0
T6	1649	0	0	0
T10	0	218	0	0
T11	0	420	0	0
T12	0	100	0	0
T13	0	286	0	0
T14	0	28	0	0
T15	0	239	0	0
T16	0	142	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172249285	11667	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172249285	11667	0	0
T1	142724	20	0	0
T2	201597	37	0	0
T3	0	12	0	0
T4	35250	0	0	0
T5	32007	0	0	0
T6	1649	0	0	0
T10	0	123	0	0
T11	0	156	0	0
T12	0	39	0	0
T13	0	160	0	0
T14	0	13	0	0
T15	0	93	0	0
T16	0	55	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	172249285	16444	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172249285	16444	0	0
T1	142724	27	0	0
T2	201597	57	0	0
T3	0	16	0	0
T4	35250	0	0	0
T5	32007	0	0	0
T6	1649	0	0	0
T10	0	159	0	0
T11	0	249	0	0
T12	0	60	0	0
T13	0	209	0	0
T14	0	18	0	0
T15	0	143	0	0
T16	0	86	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0