Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Unreachable
1	0	Covered	T1,T4,T5

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	172249285	169347268	0	0
AllClkBypReqTrue_A	172249285	140660	0	0
IoClkBypReqFalse_A	172249285	169260045	0	2415
IoClkBypReqTrue_A	172249285	223265	0	0
LcClkBypAckFalse_A	172249285	169354511	0	0
LcClkBypAckTrue_A	172249285	133417	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172249285	169347268	0	0
T1	142724	142099	0	0
T2	201597	200021	0	0
T4	35250	6464	0	0
T5	32007	2165	0	0
T6	1649	1585	0	0
T17	1574	1467	0	0
T18	1776	1709	0	0
T19	1721	1522	0	0
T20	667	650	0	0
T21	44831	3222	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172249285	140660	0	0
T1	142724	37	0	0
T2	201597	2909	0	0
T4	35250	0	0	0
T5	32007	0	0	0
T6	1649	0	0	0
T10	0	4082	0	0
T17	1574	68	0	0
T18	1776	0	0	0
T19	1721	149	0	0
T20	667	0	0	0
T21	44831	0	0	0
T26	0	116	0	0
T29	0	47	0	0
T103	0	45	0	0
T104	0	178	0	0
T105	0	240	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172249285	169260045	0	2415
T1	142724	142085	0	3
T2	201597	199912	0	3
T4	35250	6428	0	3
T5	32007	2153	0	3
T6	1649	1583	0	3
T17	1574	1490	0	3
T18	1776	1375	0	3
T19	1721	1669	0	3
T20	667	648	0	3
T21	44831	3192	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172249285	223265	0	0
T1	142724	37	0	0
T2	201597	3993	0	0
T4	35250	0	0	0
T5	32007	0	0	0
T6	1649	0	0	0
T10	0	5631	0	0
T11	0	2536	0	0
T17	1574	43	0	0
T18	1776	332	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0
T26	0	379	0	0
T29	0	181	0	0
T104	0	391	0	0
T105	0	79	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172249285	169354511	0	0
T1	142724	142104	0	0
T2	201597	200055	0	0
T4	35250	6464	0	0
T5	32007	2165	0	0
T6	1649	1585	0	0
T17	1574	1501	0	0
T18	1776	1614	0	0
T19	1721	1671	0	0
T20	667	650	0	0
T21	44831	3222	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172249285	133417	0	0
T1	142724	32	0	0
T2	201597	2575	0	0
T4	35250	0	0	0
T5	32007	0	0	0
T6	1649	0	0	0
T10	0	3416	0	0
T11	0	1267	0	0
T17	1574	34	0	0
T18	1776	95	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0
T26	0	301	0	0
T29	0	84	0	0
T104	0	210	0	0
T105	0	34	0	0