Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1874866836	16735	0	0
TransStop_A	1874866836	8631	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1874866836	16735	0	0
T1	1141800	29	0	0
T2	785732	207	0	0
T4	564012	0	0	0
T5	136196	0	0	0
T6	26408	4	0	0
T10	0	493	0	0
T11	0	90	0	0
T17	25196	0	0	0
T18	16536	0	0	0
T19	13776	0	0	0
T20	29632	0	0	0
T21	373588	0	0	0
T106	0	23	0	0
T107	0	21	0	0
T108	0	15	0	0
T109	0	4	0	0
T110	0	5	0	0
T111	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1874866836	8631	0	0
T1	1141800	16	0	0
T2	785732	111	0	0
T4	564012	0	0	0
T5	136196	0	0	0
T6	26408	4	0	0
T10	0	260	0	0
T11	0	42	0	0
T17	25196	0	0	0
T18	16536	0	0	0
T19	13776	0	0	0
T20	29632	0	0	0
T21	373588	0	0	0
T106	0	10	0	0
T107	0	12	0	0
T108	0	12	0	0
T109	0	4	0	0
T110	0	3	0	0
T111	0	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	468716709	4199	0	0
TransStop_A	468716709	2149	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716709	4199	0	0
T1	285450	7	0	0
T2	196433	46	0	0
T4	141003	0	0	0
T5	34049	0	0	0
T6	6602	1	0	0
T10	0	134	0	0
T11	0	22	0	0
T17	6299	0	0	0
T18	4134	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93397	0	0	0
T106	0	5	0	0
T107	0	5	0	0
T108	0	4	0	0
T109	0	1	0	0
T110	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716709	2149	0	0
T1	285450	3	0	0
T2	196433	24	0	0
T4	141003	0	0	0
T5	34049	0	0	0
T6	6602	1	0	0
T10	0	69	0	0
T11	0	10	0	0
T17	6299	0	0	0
T18	4134	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93397	0	0	0
T106	0	2	0	0
T107	0	3	0	0
T108	0	4	0	0
T109	0	1	0	0
T110	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	468716709	4218	0	0
TransStop_A	468716709	2143	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716709	4218	0	0
T1	285450	7	0	0
T2	196433	54	0	0
T4	141003	0	0	0
T5	34049	0	0	0
T6	6602	1	0	0
T10	0	125	0	0
T11	0	25	0	0
T17	6299	0	0	0
T18	4134	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93397	0	0	0
T106	0	5	0	0
T107	0	4	0	0
T108	0	7	0	0
T109	0	1	0	0
T110	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716709	2143	0	0
T1	285450	4	0	0
T2	196433	26	0	0
T4	141003	0	0	0
T5	34049	0	0	0
T6	6602	1	0	0
T10	0	69	0	0
T11	0	11	0	0
T17	6299	0	0	0
T18	4134	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93397	0	0	0
T106	0	2	0	0
T107	0	2	0	0
T108	0	4	0	0
T109	0	1	0	0
T110	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	468716709	4175	0	0
TransStop_A	468716709	2180	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716709	4175	0	0
T1	285450	8	0	0
T2	196433	57	0	0
T4	141003	0	0	0
T5	34049	0	0	0
T6	6602	1	0	0
T10	0	113	0	0
T11	0	23	0	0
T17	6299	0	0	0
T18	4134	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93397	0	0	0
T106	0	6	0	0
T107	0	4	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716709	2180	0	0
T1	285450	4	0	0
T2	196433	32	0	0
T4	141003	0	0	0
T5	34049	0	0	0
T6	6602	1	0	0
T10	0	61	0	0
T11	0	9	0	0
T17	6299	0	0	0
T18	4134	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93397	0	0	0
T106	0	3	0	0
T107	0	3	0	0
T108	0	1	0	0
T109	0	1	0	0
T111	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	468716709	4143	0	0
TransStop_A	468716709	2159	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716709	4143	0	0
T1	285450	7	0	0
T2	196433	50	0	0
T4	141003	0	0	0
T5	34049	0	0	0
T6	6602	1	0	0
T10	0	121	0	0
T11	0	20	0	0
T17	6299	0	0	0
T18	4134	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93397	0	0	0
T106	0	7	0	0
T107	0	8	0	0
T108	0	3	0	0
T109	0	1	0	0
T111	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716709	2159	0	0
T1	285450	5	0	0
T2	196433	29	0	0
T4	141003	0	0	0
T5	34049	0	0	0
T6	6602	1	0	0
T10	0	61	0	0
T11	0	12	0	0
T17	6299	0	0	0
T18	4134	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93397	0	0	0
T106	0	3	0	0
T107	0	4	0	0
T108	0	3	0	0
T109	0	1	0	0
T111	0	4	0	0