Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	172249285	19547014	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172249285	19547014	0	57
T1	142724	12886	0	0
T2	201597	37521	0	0
T3	0	6840	0	1
T4	35250	0	0	0
T5	32007	0	0	0
T6	1649	0	0	0
T10	0	857200	0	0
T11	0	141297	0	0
T12	0	35787	0	0
T13	0	72352	0	0
T14	0	13259	0	1
T15	0	199565	0	0
T16	0	48311	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0
T32	0	0	0	1
T50	0	0	0	1
T70	0	0	0	1
T112	0	0	0	1
T113	0	0	0	1
T114	0	0	0	1
T115	0	0	0	1
T116	0	0	0	1