Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	173109163	5718059	0	0
clk_enables_rd_A	173109163	52666	0	0
clk_hints_rd_A	173109163	46866	0	0
extclk_ctrl_rd_A	173109163	59497	0	0
extclk_ctrl_regwen_rd_A	173109163	44842	0	0
jitter_enable_rd_A	173109163	64938	0	0
jitter_regwen_rd_A	173109163	49602	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	5718059	0	0
T2	201597	60861	0	0
T3	26503	0	0	0
T10	0	149472	0	0
T11	0	96796	0	0
T13	0	107546	0	0
T15	0	28340	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0
T22	0	89517	0	0
T24	0	170787	0	0
T25	1497	0	0	0
T26	1938	0	0	0
T27	1089	0	0	0
T28	30700	0	0	0
T29	1810	0	0	0
T66	0	142519	0	0
T67	0	64526	0	0
T68	0	118563	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	52666	0	0
T2	201597	2467	0	0
T4	35250	0	0	0
T5	32007	0	0	0
T6	1649	1	0	0
T10	0	5497	0	0
T11	0	2017	0	0
T13	0	2351	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0
T24	0	6372	0	0
T25	1497	0	0	0
T66	0	5874	0	0
T85	0	2	0	0
T133	0	6	0	0
T134	0	1	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	46866	0	0
T2	201597	1954	0	0
T3	26503	0	0	0
T10	0	5084	0	0
T11	0	1699	0	0
T13	0	1899	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0
T24	0	5917	0	0
T25	1497	0	0	0
T26	1938	0	0	0
T27	1089	0	0	0
T28	30700	0	0	0
T29	1810	0	0	0
T66	0	5063	0	0
T85	0	1	0	0
T133	0	7	0	0
T135	0	6	0	0
T136	0	4	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	59497	0	0
T2	201597	2528	0	0
T3	26503	0	0	0
T10	0	6752	0	0
T11	0	2121	0	0
T13	0	2722	0	0
T18	1776	39	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0
T25	1497	0	0	0
T26	1938	31	0	0
T27	1089	0	0	0
T28	30700	0	0	0
T29	0	20	0	0
T105	0	42	0	0
T137	0	9	0	0
T138	0	24	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	44842	0	0
T2	201597	2117	0	0
T3	26503	0	0	0
T10	0	5327	0	0
T11	0	1731	0	0
T13	0	1776	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0
T24	0	6197	0	0
T25	1497	0	0	0
T26	1938	0	0	0
T27	1089	0	0	0
T28	30700	0	0	0
T29	1810	0	0	0
T47	0	35	0	0
T66	0	4835	0	0
T139	0	16	0	0
T140	0	3	0	0
T141	0	31	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	64938	0	0
T2	201597	3226	0	0
T4	35250	0	0	0
T5	32007	0	0	0
T6	1649	76	0	0
T10	0	6186	0	0
T11	0	1798	0	0
T13	0	3153	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0
T24	0	7103	0	0
T25	1497	0	0	0
T66	0	7989	0	0
T85	0	50	0	0
T133	0	74	0	0
T134	0	138	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	49602	0	0
T2	201597	2329	0	0
T3	26503	0	0	0
T10	0	5644	0	0
T11	0	2077	0	0
T13	0	2257	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	0	0	0
T24	0	6684	0	0
T25	1497	0	0	0
T26	1938	0	0	0
T27	1089	0	0	0
T28	30700	0	0	0
T29	1810	0	0	0
T66	0	5110	0	0
T142	0	3863	0	0
T143	0	3096	0	0
T144	0	4464	0	0
T145	0	2771	0	0