Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	100.00	99.31			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	100.00	99.31			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	100.00	99.31			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	100.00	99.31			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	100.00	99.31			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	100.00	99.31			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	100.00	99.31			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	100.00	99.31			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	100.00	99.31			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	100.00	99.31			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T4,T5,T2
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1731091630	1624416	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1731091630	297876	0	0
SrcBusyKnown_A	1731091630	1702485560	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1731091630	1624416	0	0
T1	1427240	2316	0	0
T2	2015970	15274	0	0
T3	0	605	0	0
T4	352500	1602	0	0
T5	320070	1070	0	0
T6	16490	0	0	0
T10	0	12494	0	0
T11	0	27806	0	0
T17	15740	0	0	0
T18	17760	0	0	0
T19	17210	0	0	0
T20	6670	0	0	0
T21	448310	2021	0	0
T28	0	680	0	0
T30	0	540	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1656348	1649860	0	0
T2	5265218	5237230	0	0
T4	817626	163462	0	0
T5	196984	14594	0	0
T6	41516	40106	0	0
T17	40386	39468	0	0
T18	26400	25482	0	0
T19	22066	21490	0	0
T20	46654	45658	0	0
T21	526064	42614	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1731091630	297876	0	0
T1	1427240	460	0	0
T2	2015970	1845	0	0
T3	0	180	0	0
T4	352500	490	0	0
T5	320070	140	0	0
T6	16490	0	0	0
T10	0	3565	0	0
T11	0	3300	0	0
T17	15740	0	0	0
T18	17760	0	0	0
T19	17210	0	0	0
T20	6670	0	0	0
T21	448310	392	0	0
T28	0	200	0	0
T30	0	120	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1731091630	1702485560	0	0
T1	1427240	1421430	0	0
T2	2015970	2003130	0	0
T4	352500	64820	0	0
T5	320070	21710	0	0
T6	16490	15860	0	0
T17	15740	15360	0	0
T18	17760	17100	0	0
T19	17210	16720	0	0
T20	6670	6510	0	0
T21	448310	32370	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173109163	101308	0	0
DstReqKnown_A	440360818	435847364	0	0
SrcAckBusyChk_A	173109163	27052	0	0
SrcBusyKnown_A	173109163	170248556	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	101308	0	0
T1	142724	164	0	0
T2	201597	939	0	0
T3	0	45	0	0
T4	35250	77	0	0
T5	32007	48	0	0
T6	1649	0	0	0
T10	0	907	0	0
T11	0	1954	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	94	0	0
T28	0	50	0	0
T30	0	39	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440360818	435847364	0	0
T1	233703	232581	0	0
T2	175898	174653	0	0
T4	135359	24828	0	0
T5	32686	2218	0	0
T6	6337	6092	0	0
T17	6047	5899	0	0
T18	3968	3820	0	0
T19	3305	3212	0	0
T20	7111	6935	0	0
T21	89657	6472	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	27052	0	0
T1	142724	46	0	0
T2	201597	182	0	0
T3	0	18	0	0
T4	35250	34	0	0
T5	32007	10	0	0
T6	1649	0	0	0
T10	0	351	0	0
T11	0	324	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	28	0	0
T28	0	20	0	0
T30	0	12	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	170248556	0	0
T1	142724	142143	0	0
T2	201597	200313	0	0
T4	35250	6482	0	0
T5	32007	2171	0	0
T6	1649	1586	0	0
T17	1574	1536	0	0
T18	1776	1710	0	0
T19	1721	1672	0	0
T20	667	651	0	0
T21	44831	3237	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173109163	148226	0	0
DstReqKnown_A	219356160	218215793	0	0
SrcAckBusyChk_A	173109163	27052	0	0
SrcBusyKnown_A	173109163	170248556	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	148226	0	0
T1	142724	230	0	0
T2	201597	1511	0	0
T3	0	65	0	0
T4	35250	113	0	0
T5	32007	75	0	0
T6	1649	0	0	0
T10	0	1268	0	0
T11	0	2766	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	132	0	0
T28	0	70	0	0
T30	0	53	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219356160	218215793	0	0
T1	116589	116326	0	0
T2	878261	874777	0	0
T4	43178	12417	0	0
T5	10277	1109	0	0
T6	3101	3046	0	0
T17	3217	3162	0	0
T18	2077	2022	0	0
T19	1755	1721	0	0
T20	3502	3468	0	0
T21	23431	3237	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	27052	0	0
T1	142724	46	0	0
T2	201597	182	0	0
T3	0	18	0	0
T4	35250	34	0	0
T5	32007	10	0	0
T6	1649	0	0	0
T10	0	351	0	0
T11	0	324	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	28	0	0
T28	0	20	0	0
T30	0	12	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	170248556	0	0
T1	142724	142143	0	0
T2	201597	200313	0	0
T4	35250	6482	0	0
T5	32007	2171	0	0
T6	1649	1586	0	0
T17	1574	1536	0	0
T18	1776	1710	0	0
T19	1721	1672	0	0
T20	667	651	0	0
T21	44831	3237	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173109163	240360	0	0
DstReqKnown_A	109677373	109107289	0	0
SrcAckBusyChk_A	173109163	27052	0	0
SrcBusyKnown_A	173109163	170248556	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	240360	0	0
T1	142724	374	0	0
T2	201597	2621	0	0
T3	0	90	0	0
T4	35250	159	0	0
T5	32007	131	0	0
T6	1649	0	0	0
T10	0	1814	0	0
T11	0	4712	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	208	0	0
T28	0	100	0	0
T30	0	88	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109677373	109107289	0	0
T1	58294	58163	0	0
T2	439125	437383	0	0
T4	21590	6209	0	0
T5	5138	554	0	0
T6	1551	1523	0	0
T17	1607	1580	0	0
T18	1039	1012	0	0
T19	876	859	0	0
T20	1751	1734	0	0
T21	11717	1620	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	27052	0	0
T1	142724	46	0	0
T2	201597	182	0	0
T3	0	18	0	0
T4	35250	34	0	0
T5	32007	10	0	0
T6	1649	0	0	0
T10	0	351	0	0
T11	0	324	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	28	0	0
T28	0	20	0	0
T30	0	12	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	170248556	0	0
T1	142724	142143	0	0
T2	201597	200313	0	0
T4	35250	6482	0	0
T5	32007	2171	0	0
T6	1649	1586	0	0
T17	1574	1536	0	0
T18	1776	1710	0	0
T19	1721	1672	0	0
T20	667	651	0	0
T21	44831	3237	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173109163	100162	0	0
DstReqKnown_A	471192794	466449428	0	0
SrcAckBusyChk_A	173109163	27052	0	0
SrcBusyKnown_A	173109163	170248556	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	100162	0	0
T1	142724	160	0	0
T2	201597	916	0	0
T3	0	44	0	0
T4	35250	77	0	0
T5	32007	46	0	0
T6	1649	0	0	0
T10	0	884	0	0
T11	0	1593	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	92	0	0
T28	0	50	0	0
T30	0	39	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471192794	466449428	0	0
T1	285450	284282	0	0
T2	196433	195136	0	0
T4	141003	25863	0	0
T5	34048	2308	0	0
T6	6601	6346	0	0
T17	6299	6144	0	0
T18	4133	3978	0	0
T19	3444	3346	0	0
T20	7408	7225	0	0
T21	93396	6741	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	27052	0	0
T1	142724	46	0	0
T2	201597	182	0	0
T3	0	18	0	0
T4	35250	34	0	0
T5	32007	10	0	0
T6	1649	0	0	0
T10	0	351	0	0
T11	0	324	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	28	0	0
T28	0	20	0	0
T30	0	12	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	170248556	0	0
T1	142724	142143	0	0
T2	201597	200313	0	0
T4	35250	6482	0	0
T5	32007	2171	0	0
T6	1649	1586	0	0
T17	1574	1536	0	0
T18	1776	1710	0	0
T19	1721	1672	0	0
T20	667	651	0	0
T21	44831	3237	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173109163	146436	0	0
DstReqKnown_A	226358070	224084571	0	0
SrcAckBusyChk_A	173109163	26588	0	0
SrcBusyKnown_A	173109163	170248556	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	146436	0	0
T1	142724	233	0	0
T2	201597	1503	0	0
T3	0	63	0	0
T4	35250	74	0	0
T5	32007	40	0	0
T6	1649	0	0	0
T10	0	1262	0	0
T11	0	2592	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	98	0	0
T28	0	70	0	0
T30	0	53	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226358070	224084571	0	0
T1	134138	133578	0	0
T2	942892	936666	0	0
T4	67683	12414	0	0
T5	16343	1108	0	0
T6	3168	3046	0	0
T17	3023	2949	0	0
T18	1983	1909	0	0
T19	1653	1607	0	0
T20	3555	3467	0	0
T21	44831	3237	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	26588	0	0
T1	142724	46	0	0
T2	201597	182	0	0
T3	0	18	0	0
T4	35250	17	0	0
T5	32007	5	0	0
T6	1649	0	0	0
T10	0	351	0	0
T11	0	324	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	14	0	0
T28	0	20	0	0
T30	0	12	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	170248556	0	0
T1	142724	142143	0	0
T2	201597	200313	0	0
T4	35250	6482	0	0
T5	32007	2171	0	0
T6	1649	1586	0	0
T17	1574	1536	0	0
T18	1776	1710	0	0
T19	1721	1672	0	0
T20	667	651	0	0
T21	44831	3237	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T4,T5,T2
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173109163	122085	0	0
DstReqKnown_A	440360818	435847364	0	0
SrcAckBusyChk_A	173109163	32735	0	0
SrcBusyKnown_A	173109163	170248556	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	122085	0	0
T1	142724	162	0	0
T2	201597	972	0	0
T3	0	43	0	0
T4	35250	159	0	0
T5	32007	95	0	0
T6	1649	0	0	0
T10	0	950	0	0
T11	0	2022	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	195	0	0
T28	0	50	0	0
T30	0	39	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440360818	435847364	0	0
T1	233703	232581	0	0
T2	175898	174653	0	0
T4	135359	24828	0	0
T5	32686	2218	0	0
T6	6337	6092	0	0
T17	6047	5899	0	0
T18	3968	3820	0	0
T19	3305	3212	0	0
T20	7111	6935	0	0
T21	89657	6472	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	32735	0	0
T1	142724	46	0	0
T2	201597	187	0	0
T3	0	18	0	0
T4	35250	68	0	0
T5	32007	20	0	0
T6	1649	0	0	0
T10	0	362	0	0
T11	0	336	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	56	0	0
T28	0	20	0	0
T30	0	12	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	170248556	0	0
T1	142724	142143	0	0
T2	201597	200313	0	0
T4	35250	6482	0	0
T5	32007	2171	0	0
T6	1649	1586	0	0
T17	1574	1536	0	0
T18	1776	1710	0	0
T19	1721	1672	0	0
T20	667	651	0	0
T21	44831	3237	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T4,T5,T2
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173109163	177733	0	0
DstReqKnown_A	219356160	218215793	0	0
SrcAckBusyChk_A	173109163	32625	0	0
SrcBusyKnown_A	173109163	170248556	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	177733	0	0
T1	142724	228	0	0
T2	201597	1558	0	0
T3	0	62	0	0
T4	35250	231	0	0
T5	32007	149	0	0
T6	1649	0	0	0
T10	0	1303	0	0
T11	0	2850	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	278	0	0
T28	0	70	0	0
T30	0	53	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219356160	218215793	0	0
T1	116589	116326	0	0
T2	878261	874777	0	0
T4	43178	12417	0	0
T5	10277	1109	0	0
T6	3101	3046	0	0
T17	3217	3162	0	0
T18	2077	2022	0	0
T19	1755	1721	0	0
T20	3502	3468	0	0
T21	23431	3237	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	32625	0	0
T1	142724	46	0	0
T2	201597	187	0	0
T3	0	18	0	0
T4	35250	68	0	0
T5	32007	20	0	0
T6	1649	0	0	0
T10	0	362	0	0
T11	0	336	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	56	0	0
T28	0	20	0	0
T30	0	12	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	170248556	0	0
T1	142724	142143	0	0
T2	201597	200313	0	0
T4	35250	6482	0	0
T5	32007	2171	0	0
T6	1649	1586	0	0
T17	1574	1536	0	0
T18	1776	1710	0	0
T19	1721	1672	0	0
T20	667	651	0	0
T21	44831	3237	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T4,T5,T2
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173109163	289856	0	0
DstReqKnown_A	109677373	109107289	0	0
SrcAckBusyChk_A	173109163	32672	0	0
SrcBusyKnown_A	173109163	170248556	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	289856	0	0
T1	142724	372	0	0
T2	201597	2749	0	0
T3	0	87	0	0
T4	35250	328	0	0
T5	32007	268	0	0
T6	1649	0	0	0
T10	0	1890	0	0
T11	0	4957	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	439	0	0
T28	0	100	0	0
T30	0	86	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109677373	109107289	0	0
T1	58294	58163	0	0
T2	439125	437383	0	0
T4	21590	6209	0	0
T5	5138	554	0	0
T6	1551	1523	0	0
T17	1607	1580	0	0
T18	1039	1012	0	0
T19	876	859	0	0
T20	1751	1734	0	0
T21	11717	1620	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	32672	0	0
T1	142724	46	0	0
T2	201597	187	0	0
T3	0	18	0	0
T4	35250	68	0	0
T5	32007	20	0	0
T6	1649	0	0	0
T10	0	362	0	0
T11	0	336	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	56	0	0
T28	0	20	0	0
T30	0	12	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	170248556	0	0
T1	142724	142143	0	0
T2	201597	200313	0	0
T4	35250	6482	0	0
T5	32007	2171	0	0
T6	1649	1586	0	0
T17	1574	1536	0	0
T18	1776	1710	0	0
T19	1721	1672	0	0
T20	667	651	0	0
T21	44831	3237	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T4,T5,T2
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173109163	119934	0	0
DstReqKnown_A	471192794	466449428	0	0
SrcAckBusyChk_A	173109163	32575	0	0
SrcBusyKnown_A	173109163	170248556	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	119934	0	0
T1	142724	159	0	0
T2	201597	944	0	0
T3	0	43	0	0
T4	35250	158	0	0
T5	32007	94	0	0
T6	1649	0	0	0
T10	0	914	0	0
T11	0	1656	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	191	0	0
T28	0	50	0	0
T30	0	37	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	471192794	466449428	0	0
T1	285450	284282	0	0
T2	196433	195136	0	0
T4	141003	25863	0	0
T5	34048	2308	0	0
T6	6601	6346	0	0
T17	6299	6144	0	0
T18	4133	3978	0	0
T19	3444	3346	0	0
T20	7408	7225	0	0
T21	93396	6741	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	32575	0	0
T1	142724	46	0	0
T2	201597	187	0	0
T3	0	18	0	0
T4	35250	68	0	0
T5	32007	20	0	0
T6	1649	0	0	0
T10	0	362	0	0
T11	0	336	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	56	0	0
T28	0	20	0	0
T30	0	12	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	170248556	0	0
T1	142724	142143	0	0
T2	201597	200313	0	0
T4	35250	6482	0	0
T5	32007	2171	0	0
T6	1649	1586	0	0
T17	1574	1536	0	0
T18	1776	1710	0	0
T19	1721	1672	0	0
T20	667	651	0	0
T21	44831	3237	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Covered	T4,T5,T2
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T4
0	1	Unreachable
1	0	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T6,T4
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	173109163	178316	0	0
DstReqKnown_A	226358070	224084571	0	0
SrcAckBusyChk_A	173109163	32473	0	0
SrcBusyKnown_A	173109163	170248556	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	178316	0	0
T1	142724	234	0	0
T2	201597	1561	0	0
T3	0	63	0	0
T4	35250	226	0	0
T5	32007	124	0	0
T6	1649	0	0	0
T10	0	1302	0	0
T11	0	2704	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	294	0	0
T28	0	70	0	0
T30	0	53	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226358070	224084571	0	0
T1	134138	133578	0	0
T2	942892	936666	0	0
T4	67683	12414	0	0
T5	16343	1108	0	0
T6	3168	3046	0	0
T17	3023	2949	0	0
T18	1983	1909	0	0
T19	1653	1607	0	0
T20	3555	3467	0	0
T21	44831	3237	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	32473	0	0
T1	142724	46	0	0
T2	201597	187	0	0
T3	0	18	0	0
T4	35250	65	0	0
T5	32007	15	0	0
T6	1649	0	0	0
T10	0	362	0	0
T11	0	336	0	0
T17	1574	0	0	0
T18	1776	0	0	0
T19	1721	0	0	0
T20	667	0	0	0
T21	44831	42	0	0
T28	0	20	0	0
T30	0	12	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173109163	170248556	0	0
T1	142724	142143	0	0
T2	201597	200313	0	0
T4	35250	6482	0	0
T5	32007	2171	0	0
T6	1649	1586	0	0
T17	1574	1536	0	0
T18	1776	1710	0	0
T19	1721	1672	0	0
T20	667	651	0	0
T21	44831	3237	0	0