Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	49640	0	0
CgEnOn_A	2147483647	40404	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49640	0	0
T1	979486	47	0	0
T2	1886150	173	0	0
T4	482133	54	0	0
T5	116197	18	0	0
T6	24191	7	0	0
T11	2522278	27	0	0
T17	23469	3	0	0
T18	15350	3	0	0
T19	12824	3	0	0
T20	27180	17	0	0
T21	311597	45	0	0
T30	135960	0	0	0
T36	1502	5	0	0
T37	0	20	0	0
T38	0	30	0	0
T39	0	15	0	0
T66	0	5	0	0
T106	0	5	0	0
T109	3784	0	0	0
T110	5075	0	0	0
T111	11928	0	0	0
T137	3520	0	0	0
T138	5965	0	0	0
T146	0	25	0	0
T147	0	30	0	0
T148	0	15	0	0
T149	0	5	0	0
T157	18860	0	0	0
T158	3526	0	0	0
T159	3585	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40404	0	0
T1	174883	26	0	0
T2	1317386	155	0	0
T4	64768	0	0	0
T5	15415	0	0	0
T6	4652	4	0	0
T10	0	427	0	0
T11	2239854	357	0	0
T17	4824	0	0	0
T18	3116	0	0	0
T19	2631	0	0	0
T20	5253	14	0	0
T21	35148	0	0	0
T30	75490	0	0	0
T36	1446	8	0	0
T37	0	24	0	0
T38	0	30	0	0
T39	0	15	0	0
T66	0	4	0	0
T106	0	5	0	0
T109	2050	3	0	0
T110	2760	0	0	0
T111	6590	0	0	0
T137	1960	0	0	0
T138	3470	0	0	0
T146	0	25	0	0
T147	0	30	0	0
T148	0	15	0	0
T149	0	5	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	34	0	0
T157	10580	0	0	0
T158	1930	0	0	0
T159	1940	0	0	0
T160	0	23	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	218212595	163	0	0
CgEnOn_A	218212595	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218212595	163	0	0
T11	139992	1	0	0
T30	30196	0	0	0
T36	0	1	0	0
T37	0	4	0	0
T38	0	6	0	0
T39	0	3	0	0
T66	0	1	0	0
T109	820	0	0	0
T110	1104	0	0	0
T111	2636	0	0	0
T137	784	0	0	0
T138	1388	0	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	1	0	0
T157	4232	0	0	0
T158	772	0	0	0
T159	776	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218212595	163	0	0
T11	139992	1	0	0
T30	30196	0	0	0
T36	0	1	0	0
T37	0	4	0	0
T38	0	6	0	0
T39	0	3	0	0
T66	0	1	0	0
T109	820	0	0	0
T110	1104	0	0	0
T111	2636	0	0	0
T137	784	0	0	0
T138	1388	0	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	1	0	0
T157	4232	0	0	0
T158	772	0	0	0
T159	776	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	109105596	163	0	0
CgEnOn_A	109105596	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109105596	163	0	0
T11	699954	1	0	0
T30	15098	0	0	0
T36	0	1	0	0
T37	0	4	0	0
T38	0	6	0	0
T39	0	3	0	0
T66	0	1	0	0
T109	410	0	0	0
T110	552	0	0	0
T111	1318	0	0	0
T137	392	0	0	0
T138	694	0	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	1	0	0
T157	2116	0	0	0
T158	386	0	0	0
T159	388	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109105596	163	0	0
T11	699954	1	0	0
T30	15098	0	0	0
T36	0	1	0	0
T37	0	4	0	0
T38	0	6	0	0
T39	0	3	0	0
T66	0	1	0	0
T109	410	0	0	0
T110	552	0	0	0
T111	1318	0	0	0
T137	392	0	0	0
T138	694	0	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	1	0	0
T157	2116	0	0	0
T158	386	0	0	0
T159	388	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	437983444	163	0	0
CgEnOn_A	437983444	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437983444	163	0	0
T11	282424	1	0	0
T30	60470	0	0	0
T36	0	1	0	0
T37	0	4	0	0
T38	0	6	0	0
T39	0	3	0	0
T66	0	1	0	0
T109	1734	0	0	0
T110	2315	0	0	0
T111	5338	0	0	0
T137	1560	0	0	0
T138	2495	0	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	1	0	0
T157	8280	0	0	0
T158	1596	0	0	0
T159	1645	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437983444	155	0	0
T13	129501	0	0	0
T14	123076	0	0	0
T15	745858	0	0	0
T36	1446	1	0	0
T37	1468	4	0	0
T38	1781	6	0	0
T39	0	3	0	0
T133	2424	0	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	2567	0	0	0
T153	2027	0	0	0
T154	4315	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	468716257	146	0	0
CgEnOn_A	468716257	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716257	146	0	0
T13	139342	1	0	0
T14	128207	0	0	0
T15	782958	0	0	0
T36	1502	1	0	0
T37	1416	4	0	0
T38	1785	5	0	0
T39	0	4	0	0
T133	2525	0	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	3	0	0
T149	0	3	0	0
T150	0	2	0	0
T152	2674	0	0	0
T153	2113	0	0	0
T154	4494	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716257	144	0	0
T13	139342	0	0	0
T14	128207	0	0	0
T15	782958	0	0	0
T36	1502	1	0	0
T37	1416	4	0	0
T38	1785	5	0	0
T39	0	4	0	0
T133	2525	0	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	3	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	2674	0	0	0
T153	2113	0	0	0
T154	4494	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	109105596	163	0	0
CgEnOn_A	109105596	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109105596	163	0	0
T11	699954	1	0	0
T30	15098	0	0	0
T36	0	1	0	0
T37	0	4	0	0
T38	0	6	0	0
T39	0	3	0	0
T66	0	1	0	0
T109	410	0	0	0
T110	552	0	0	0
T111	1318	0	0	0
T137	392	0	0	0
T138	694	0	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	1	0	0
T157	2116	0	0	0
T158	386	0	0	0
T159	388	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109105596	163	0	0
T11	699954	1	0	0
T30	15098	0	0	0
T36	0	1	0	0
T37	0	4	0	0
T38	0	6	0	0
T39	0	3	0	0
T66	0	1	0	0
T109	410	0	0	0
T110	552	0	0	0
T111	1318	0	0	0
T137	392	0	0	0
T138	694	0	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	1	0	0
T157	2116	0	0	0
T158	386	0	0	0
T159	388	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	468716257	146	0	0
CgEnOn_A	468716257	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716257	146	0	0
T13	139342	1	0	0
T14	128207	0	0	0
T15	782958	0	0	0
T36	1502	1	0	0
T37	1416	4	0	0
T38	1785	5	0	0
T39	0	4	0	0
T133	2525	0	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	3	0	0
T149	0	3	0	0
T150	0	2	0	0
T152	2674	0	0	0
T153	2113	0	0	0
T154	4494	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716257	144	0	0
T13	139342	0	0	0
T14	128207	0	0	0
T15	782958	0	0	0
T36	1502	1	0	0
T37	1416	4	0	0
T38	1785	5	0	0
T39	0	4	0	0
T133	2525	0	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	3	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	2674	0	0	0
T153	2113	0	0	0
T154	4494	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	109105596	163	0	0
CgEnOn_A	109105596	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109105596	163	0	0
T11	699954	1	0	0
T30	15098	0	0	0
T36	0	1	0	0
T37	0	4	0	0
T38	0	6	0	0
T39	0	3	0	0
T66	0	1	0	0
T109	410	0	0	0
T110	552	0	0	0
T111	1318	0	0	0
T137	392	0	0	0
T138	694	0	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	1	0	0
T157	2116	0	0	0
T158	386	0	0	0
T159	388	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109105596	163	0	0
T11	699954	1	0	0
T30	15098	0	0	0
T36	0	1	0	0
T37	0	4	0	0
T38	0	6	0	0
T39	0	3	0	0
T66	0	1	0	0
T109	410	0	0	0
T110	552	0	0	0
T111	1318	0	0	0
T137	392	0	0	0
T138	694	0	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	1	0	0
T157	2116	0	0	0
T158	386	0	0	0
T159	388	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	218212595	7842	0	0
CgEnOn_A	218212595	5542	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218212595	7842	0	0
T1	116589	13	0	0
T2	878261	44	0	0
T4	43178	18	0	0
T5	10277	6	0	0
T6	3101	2	0	0
T17	3217	1	0	0
T18	2077	1	0	0
T19	1755	1	0	0
T20	3502	5	0	0
T21	23431	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218212595	5542	0	0
T1	116589	6	0	0
T2	878261	38	0	0
T4	43178	0	0	0
T5	10277	0	0	0
T6	3101	1	0	0
T10	0	99	0	0
T11	0	109	0	0
T17	3217	0	0	0
T18	2077	0	0	0
T19	1755	0	0	0
T20	3502	4	0	0
T21	23431	0	0	0
T36	0	1	0	0
T109	0	1	0	0
T152	0	11	0	0
T160	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	109105596	7740	0	0
CgEnOn_A	109105596	5440	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109105596	7740	0	0
T1	58294	13	0	0
T2	439125	41	0	0
T4	21590	18	0	0
T5	5138	6	0	0
T6	1551	2	0	0
T17	1607	1	0	0
T18	1039	1	0	0
T19	876	1	0	0
T20	1751	6	0	0
T21	11717	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109105596	5440	0	0
T1	58294	6	0	0
T2	439125	35	0	0
T4	21590	0	0	0
T5	5138	0	0	0
T6	1551	1	0	0
T10	0	99	0	0
T11	0	111	0	0
T17	1607	0	0	0
T18	1039	0	0	0
T19	876	0	0	0
T20	1751	5	0	0
T21	11717	0	0	0
T36	0	1	0	0
T37	0	4	0	0
T152	0	12	0	0
T160	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	437983444	7809	0	0
CgEnOn_A	437983444	5501	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437983444	7809	0	0
T1	233703	14	0	0
T2	175898	42	0	0
T4	135359	18	0	0
T5	32686	6	0	0
T6	6337	2	0	0
T17	6047	1	0	0
T18	3968	1	0	0
T19	3305	1	0	0
T20	7111	6	0	0
T21	89657	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437983444	5501	0	0
T1	233703	7	0	0
T2	175898	36	0	0
T4	135359	0	0	0
T5	32686	0	0	0
T6	6337	1	0	0
T10	0	95	0	0
T11	0	111	0	0
T17	6047	0	0	0
T18	3968	0	0	0
T19	3305	0	0	0
T20	7111	5	0	0
T21	89657	0	0	0
T36	0	1	0	0
T109	0	1	0	0
T152	0	11	0	0
T160	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	225169357	7823	0	0
CgEnOn_A	225169357	5515	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225169357	7823	0	0
T1	134138	14	0	0
T2	942892	43	0	0
T4	67683	18	0	0
T5	16343	6	0	0
T6	3168	2	0	0
T17	3023	1	0	0
T18	1983	1	0	0
T19	1653	1	0	0
T20	3555	6	0	0
T21	44831	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225169357	5515	0	0
T1	134138	7	0	0
T2	942892	37	0	0
T4	67683	0	0	0
T5	16343	0	0	0
T6	3168	1	0	0
T10	0	101	0	0
T11	0	110	0	0
T17	3023	0	0	0
T18	1983	0	0	0
T19	1653	0	0	0
T20	3555	5	0	0
T21	44831	0	0	0
T37	0	5	0	0
T109	0	1	0	0
T152	0	10	0	0
T160	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	468716257	4345	0	0
CgEnOn_A	468716257	4343	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716257	4345	0	0
T1	285450	7	0	0
T2	196433	46	0	0
T4	141003	0	0	0
T5	34048	0	0	0
T6	6601	1	0	0
T10	0	134	0	0
T11	0	22	0	0
T17	6299	0	0	0
T18	4133	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93396	0	0	0
T106	0	5	0	0
T107	0	5	0	0
T108	0	4	0	0
T109	0	1	0	0
T110	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716257	4343	0	0
T1	285450	7	0	0
T2	196433	46	0	0
T4	141003	0	0	0
T5	34048	0	0	0
T6	6601	1	0	0
T10	0	134	0	0
T11	0	22	0	0
T17	6299	0	0	0
T18	4133	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93396	0	0	0
T106	0	5	0	0
T107	0	5	0	0
T108	0	4	0	0
T109	0	1	0	0
T110	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	468716257	4364	0	0
CgEnOn_A	468716257	4362	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716257	4364	0	0
T1	285450	7	0	0
T2	196433	54	0	0
T4	141003	0	0	0
T5	34048	0	0	0
T6	6601	1	0	0
T10	0	125	0	0
T11	0	25	0	0
T17	6299	0	0	0
T18	4133	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93396	0	0	0
T106	0	5	0	0
T107	0	4	0	0
T108	0	7	0	0
T109	0	1	0	0
T110	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716257	4362	0	0
T1	285450	7	0	0
T2	196433	54	0	0
T4	141003	0	0	0
T5	34048	0	0	0
T6	6601	1	0	0
T10	0	125	0	0
T11	0	25	0	0
T17	6299	0	0	0
T18	4133	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93396	0	0	0
T106	0	5	0	0
T107	0	4	0	0
T108	0	7	0	0
T109	0	1	0	0
T110	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	468716257	4321	0	0
CgEnOn_A	468716257	4319	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716257	4321	0	0
T1	285450	8	0	0
T2	196433	57	0	0
T4	141003	0	0	0
T5	34048	0	0	0
T6	6601	1	0	0
T10	0	113	0	0
T11	0	23	0	0
T17	6299	0	0	0
T18	4133	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93396	0	0	0
T106	0	6	0	0
T107	0	4	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716257	4319	0	0
T1	285450	8	0	0
T2	196433	57	0	0
T4	141003	0	0	0
T5	34048	0	0	0
T6	6601	1	0	0
T10	0	113	0	0
T11	0	23	0	0
T17	6299	0	0	0
T18	4133	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93396	0	0	0
T106	0	6	0	0
T107	0	4	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	468716257	4289	0	0
CgEnOn_A	468716257	4287	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716257	4289	0	0
T1	285450	7	0	0
T2	196433	50	0	0
T4	141003	0	0	0
T5	34048	0	0	0
T6	6601	1	0	0
T10	0	121	0	0
T11	0	20	0	0
T17	6299	0	0	0
T18	4133	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93396	0	0	0
T106	0	7	0	0
T107	0	8	0	0
T108	0	3	0	0
T109	0	1	0	0
T111	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468716257	4287	0	0
T1	285450	7	0	0
T2	196433	50	0	0
T4	141003	0	0	0
T5	34048	0	0	0
T6	6601	1	0	0
T10	0	121	0	0
T11	0	20	0	0
T17	6299	0	0	0
T18	4133	0	0	0
T19	3444	0	0	0
T20	7408	0	0	0
T21	93396	0	0	0
T106	0	7	0	0
T107	0	8	0	0
T108	0	3	0	0
T109	0	1	0	0
T111	0	9	0	0