Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 332776158 1 T4 1596 T1 227468 T5 3652
auto[1] 422084 1 T1 1046 T17 200 T20 850


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 332776736 1 T4 1596 T1 227614 T5 3652
auto[1] 421506 1 T1 900 T20 482 T32 432


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 332690678 1 T4 1596 T1 227462 T5 3652
auto[1] 507564 1 T1 1052 T17 190 T20 748


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 307035878 1 T4 1596 T1 221912 T5 3652
auto[1] 26162364 1 T1 6602 T17 2528 T20 4158


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 188167930 1 T4 1596 T1 130190 T5 3632
auto[1] 145030312 1 T1 98324 T5 20 T15 1344


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 166937930 1 T4 1596 T1 123232 T5 3632
auto[0] auto[0] auto[0] auto[0] auto[1] 139752768 1 T1 98178 T5 20 T15 1344
auto[0] auto[0] auto[0] auto[1] auto[0] 30814 1 T1 48 T20 40 T32 50
auto[0] auto[0] auto[0] auto[1] auto[1] 8188 1 T32 2 T3 222 T62 22
auto[0] auto[0] auto[1] auto[0] auto[0] 20629398 1 T1 5510 T17 2298 T20 3206
auto[0] auto[0] auto[1] auto[0] auto[1] 5156294 1 T1 60 T20 94 T55 100
auto[0] auto[0] auto[1] auto[1] auto[0] 53172 1 T1 98 T17 40 T20 184
auto[0] auto[0] auto[1] auto[1] auto[1] 13824 1 T1 14 T20 24 T55 10
auto[0] auto[1] auto[0] auto[0] auto[0] 56198 1 T1 34 T32 16 T55 18
auto[0] auto[1] auto[0] auto[0] auto[1] 1692 1 T3 6 T10 20 T143 2
auto[0] auto[1] auto[0] auto[1] auto[0] 10758 1 T1 140 T55 70 T8 60
auto[0] auto[1] auto[0] auto[1] auto[1] 3386 1 T3 72 T143 78 T14 68
auto[0] auto[1] auto[1] auto[0] auto[0] 11160 1 T1 82 T32 8 T55 2
auto[0] auto[1] auto[1] auto[0] auto[1] 3072 1 T55 18 T3 18 T10 16
auto[0] auto[1] auto[1] auto[1] auto[0] 17428 1 T1 66 T55 100 T3 446
auto[0] auto[1] auto[1] auto[1] auto[1] 4596 1 T55 90 T3 64 T10 66
auto[1] auto[0] auto[0] auto[0] auto[0] 40396 1 T1 22 T32 36 T55 20
auto[1] auto[0] auto[0] auto[0] auto[1] 4442 1 T55 66 T3 92 T167 8
auto[1] auto[0] auto[0] auto[1] auto[0] 33268 1 T1 182 T32 202 T55 88
auto[1] auto[0] auto[0] auto[1] auto[1] 7518 1 T3 162 T10 88 T136 78
auto[1] auto[0] auto[1] auto[0] auto[0] 30286 1 T1 60 T17 30 T20 8
auto[1] auto[0] auto[1] auto[0] auto[1] 8058 1 T1 12 T20 12 T3 208
auto[1] auto[0] auto[1] auto[1] auto[0] 56216 1 T1 138 T17 160 T20 164
auto[1] auto[0] auto[1] auto[1] auto[1] 14164 1 T1 60 T20 82 T3 124
auto[1] auto[1] auto[0] auto[0] auto[0] 80074 1 T1 76 T20 20 T32 76
auto[1] auto[1] auto[0] auto[0] auto[1] 6602 1 T20 24 T32 16 T3 88
auto[1] auto[1] auto[0] auto[1] auto[0] 48538 1 T20 54 T32 212 T55 84
auto[1] auto[1] auto[0] auto[1] auto[1] 13306 1 T32 104 T3 448 T8 64
auto[1] auto[1] auto[1] auto[0] auto[0] 46764 1 T1 202 T20 82 T55 26
auto[1] auto[1] auto[1] auto[0] auto[1] 11024 1 T3 94 T8 58 T61 8
auto[1] auto[1] auto[1] auto[1] auto[0] 85530 1 T1 300 T20 302 T55 156
auto[1] auto[1] auto[1] auto[1] auto[1] 21378 1 T3 294 T8 56 T61 66

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