---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_io_div2_meas.u_meas.MaxWidth_A	0	0	229938236	0	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	17529319	0	0	0
tb.dut.u_io_div4_meas.u_meas.MaxWidth_A	0	0	114968483	0	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	17529319	0	0	0
tb.dut.u_io_meas.u_meas.MaxWidth_A	0	0	457385032	0	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	17529319	0	0	0
tb.dut.u_main_meas.u_meas.MaxWidth_A	0	0	487104382	0	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	17529319	0	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	231299016	0	0	1010
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	115648874	0	0	1010
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	460199019	0	0	1010
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	490035738	0	0	1010
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	235343874	0	0	1010
tb.dut.u_usb_meas.u_meas.MaxWidth_A	0	0	233936852	0	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	17529319	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnownO_A	0	0	168225665	165719583	0	0
tb.dut.AllClkBypReqKnownO_A	0	0	168225665	165719583	0	0
tb.dut.CgEnKnownO_A	0	0	168225665	165719583	0	0
tb.dut.ClocksKownO_A	0	0	168225665	165719583	0	0
tb.dut.FpvSecCmClkMainAesCountCheck_A	0	0	168225665	26	0	0
tb.dut.FpvSecCmClkMainHmacCountCheck_A	0	0	168225665	25	0	0
tb.dut.FpvSecCmClkMainKmacCountCheck_A	0	0	168225665	26	0	0
tb.dut.FpvSecCmClkMainOtbnCountCheck_A	0	0	168225665	27	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	168225665	50	0	0
tb.dut.IoClkBypReqKnownO_A	0	0	168225665	165719583	0	0
tb.dut.JitterEnableKnownO_A	0	0	168225665	165719583	0	0
tb.dut.LcCtrlClkBypAckKnownO_A	0	0	168225665	165719583	0	0
tb.dut.PwrMgrKnownO_A	0	0	168225665	165719583	0	0
tb.dut.TlAReadyKnownO_A	0	0	168225665	165719583	0	0
tb.dut.TlDValidKnownO_A	0	0	168225665	165719583	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStart_A	0	0	487104832	3853	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStop_A	0	0	487104832	1944	0	0
tb.dut.clkmgr_aon_cg_aon_peri.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_secure.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_timers.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_div2_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_div4_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_main_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_usb_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOff_A	0	0	229938236	141	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOn_A	0	0	229938236	141	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOff_A	0	0	229938236	7718	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOn_A	0	0	229938236	5518	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOff_A	0	0	114968483	141	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOn_A	0	0	114968483	141	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOff_A	0	0	114968483	7688	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOn_A	0	0	114968483	5488	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOff_A	0	0	114968483	141	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOn_A	0	0	114968483	141	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOff_A	0	0	114968483	141	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOn_A	0	0	114968483	141	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOff_A	0	0	457385032	141	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOn_A	0	0	457385032	135	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOff_A	0	0	457385032	7748	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOn_A	0	0	457385032	5542	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOff_A	0	0	487104382	3994	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOn_A	0	0	487104382	3991	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOff_A	0	0	487104382	4026	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOn_A	0	0	487104382	4023	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOff_A	0	0	487104382	141	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOn_A	0	0	487104382	138	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOff_A	0	0	487104382	4034	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOn_A	0	0	487104382	4031	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOff_A	0	0	487104382	4003	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOn_A	0	0	487104382	4000	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOff_A	0	0	487104382	141	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOn_A	0	0	487104382	138	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOff_A	0	0	233936852	7742	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOn_A	0	0	233936852	5534	0	0
tb.dut.clkmgr_csr_assert.TlulOOBAddrErr_A	0	0	169203733	5891520	0	0
tb.dut.clkmgr_csr_assert.clk_enables_rd_A	0	0	169203733	32677	0	0
tb.dut.clkmgr_csr_assert.clk_hints_rd_A	0	0	169203733	29209	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_rd_A	0	0	169203733	34202	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_regwen_rd_A	0	0	169203733	27760	0	0
tb.dut.clkmgr_csr_assert.jitter_enable_rd_A	0	0	169203733	40917	0	0
tb.dut.clkmgr_csr_assert.jitter_regwen_rd_A	0	0	169203733	30743	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Stepped_A	0	0	457385469	4411	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Whole_A	0	0	457385469	5337	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Stepped_A	0	0	229938648	4311	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Whole_A	0	0	229938648	4981	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqFall_A	0	0	168225665	4278	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqRise_A	0	0	168225665	4278	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelFall_A	0	0	168225665	2562	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelRise_A	0	0	168225665	2562	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqFall_A	0	0	168225665	5279	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqRise_A	0	0	168225665	5279	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStart_A	0	0	487104832	3885	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStop_A	0	0	487104832	1937	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateClose_A	0	0	229938648	3584	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateOpen_A	0	0	229938648	5110	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateClose_A	0	0	114968883	3339	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateOpen_A	0	0	114968883	4865	0	0
tb.dut.clkmgr_io_peri_sva_if.GateClose_A	0	0	457385469	3624	0	0
tb.dut.clkmgr_io_peri_sva_if.GateOpen_A	0	0	457385469	5153	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStart_A	0	0	487104832	3893	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStop_A	0	0	487104832	1930	0	0
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if.CtrlEnOn_A	0	0	168225665	11627	0	0
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if.CtrlEnOn_A	0	0	168225665	16073	0	0
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if.CtrlEnOn_A	0	0	168225665	24663	0	0
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if.CtrlEnOn_A	0	0	168225665	11393	0	0
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	168225665	25054874	0	58
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if.CtrlEnOn_A	0	0	168225665	16058	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStart_A	0	0	487104832	3862	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStop_A	0	0	487104832	1953	0	0
tb.dut.clkmgr_pwrmgr_sva_if.IoStatusFall_A	0	0	168225665	132	0	0
tb.dut.clkmgr_pwrmgr_sva_if.IoStatusRise_A	0	0	168225665	132	0	0
tb.dut.clkmgr_pwrmgr_sva_if.MainStatusFall_A	0	0	168225665	137	0	0
tb.dut.clkmgr_pwrmgr_sva_if.MainStatusRise_A	0	0	168225665	137	0	0
tb.dut.clkmgr_pwrmgr_sva_if.UsbStatusFall_A	0	0	168225665	137	0	0
tb.dut.clkmgr_pwrmgr_sva_if.UsbStatusRise_A	0	0	168225665	137	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqFalse_A	0	0	168225665	165580664	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqTrue_A	0	0	168225665	136710	0	0
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	168225665	165501914	0	2415
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqTrue_A	0	0	168225665	211042	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckFalse_A	0	0	168225665	165593644	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckTrue_A	0	0	168225665	123730	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateClose_A	0	0	233937276	3588	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateOpen_A	0	0	233937276	5118	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	169203733	22764543	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	169203733	166599121	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	169203733	166599121	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	169203733	19279576	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	169203733	166599121	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	169203733	166599121	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
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tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	169204353	18790809	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	169203733	3182894	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	169204353	208926	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	169204353	129317	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	169203733	3522126	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	169204353	22764543	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	169204353	19279576	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	169204353	22764543	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	169204353	19279576	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	169204353	19279576	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	169204353	19279576	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	169203733	1899440	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	169203733	1451666	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1010	1010	0	0
tb.dut.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_calib_rdy_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_clk_io_div2_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	168225665	165719583	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	168225665	165719583	0	0
tb.dut.u_clk_io_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_peri_scanmode_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_clk_io_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	168225665	165719583	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.OutputsKnown_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	487104382	482514370	0	2415
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	487104382	32796	0	0
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.OutputsKnown_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.OutputsKnown_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	487104382	482514370	0	2415
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	487104382	33160	0	0
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.OutputsKnown_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	487104382	482514370	0	2415
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	487104382	32923	0	0
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.OutputsKnown_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	487104382	482514370	0	2415
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	487104382	33016	0	0
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.OutputsKnown_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	487104382	482521034	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	168225665	165719583	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	168225665	20129	0	0
tb.dut.u_clkmgr_byp.u_all_byp_req.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_clkmgr_byp.u_en_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_en_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_clkmgr_byp.u_hi_speed_sel.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	168225665	17476	0	0
tb.dut.u_clkmgr_byp.u_io_byp_req.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_io_div2_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_div_scanmode_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_io_div2_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	168225665	165719583	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	168225665	2936	0	0
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckHoldReq	0	0	229938236	2936	0	0
tb.dut.u_io_div2_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	229938236	3884332	0	0
tb.dut.u_io_div2_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	229938236	90308	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	17425717	89206	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	229938236	229938236	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	229938236	229938236	0	0
tb.dut.u_io_div4_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_div_scanmode_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_io_div4_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	168225665	165719583	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	168225665	2807	0	0
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckHoldReq	0	0	114968483	2807	0	0
tb.dut.u_io_div4_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	114968483	3704125	0	0
tb.dut.u_io_div4_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	114968483	89475	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	17425717	88380	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	114968483	114968483	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	114968483	114968483	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_io_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	168225665	2887	0	0
tb.dut.u_io_meas.u_err_sync.SyncReqAckHoldReq	0	0	457385032	2887	0	0
tb.dut.u_io_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	457385032	3884431	0	0
tb.dut.u_io_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	457385032	90791	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	17425717	89688	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	457385032	455201295	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	457385032	455201295	0	0
tb.dut.u_io_step_down_req_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_step_down_req_sync.OutputsKnown_A	0	0	457385032	453049813	0	0
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	457385032	453043186	0	2415
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	457385032	28252	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_main_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	168225665	2886	0	0
tb.dut.u_main_meas.u_err_sync.SyncReqAckHoldReq	0	0	487104382	2886	0	0
tb.dut.u_main_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	487104382	3888498	0	0
tb.dut.u_main_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	487104382	109708	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	17510940	109187	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	487104382	484795186	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	487104382	484795186	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.DivEven_A	0	0	805	805	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown0	0	0	227601192	227600387	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown1	0	0	457385032	457384227	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	229938236	229937431	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	457385032	457384227	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.DivEven_A	0	0	805	805	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	114968483	114967678	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	457385032	457384227	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra.OutputsKnown_A	0	0	229938236	228862039	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri.OutputsKnown_A	0	0	229938236	228862039	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra.OutputsKnown_A	0	0	114968483	114430456	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri.OutputsKnown_A	0	0	114968483	114430456	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure.OutputsKnown_A	0	0	114968483	114430456	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.OutputsKnown_A	0	0	114968483	114430456	0	0
tb.dut.u_prim_mubi4_sender_clk_io_infra.OutputsKnown_A	0	0	457385032	453049813	0	0
tb.dut.u_prim_mubi4_sender_clk_io_peri.OutputsKnown_A	0	0	457385032	453049813	0	0
tb.dut.u_prim_mubi4_sender_clk_main_infra.OutputsKnown_A	0	0	487104382	482521034	0	0
tb.dut.u_prim_mubi4_sender_clk_main_secure.OutputsKnown_A	0	0	487104382	482521034	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_infra.OutputsKnown_A	0	0	233936852	231739792	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_peri.OutputsKnown_A	0	0	233936852	231739792	0	0
tb.dut.u_reg.en2addrHit	0	0	169203733	869318	0	0
tb.dut.u_reg.reAfterRv	0	0	169203733	869318	0	0
tb.dut.u_reg.rePulse	0	0	169203733	202778	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	169203733	136063	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.DstReqKnown_A	0	0	231299016	230176215	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	169203733	24715	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	169203733	166599121	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	231299016	1144	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	169203733	25859	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	231299016	24715	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	231299016	24715	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	169203733	24715	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	169203733	171800	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	231299016	230176215	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	169203733	30843	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	169203733	166599121	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	169203733	30842	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	231299016	30845	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	231299016	30845	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	169203733	30866	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	231299016	230176215	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	169203733	40	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	231299016	40	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	231299016	230176215	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	169203733	39	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	231299016	39	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	169203733	220662	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.DstReqKnown_A	0	0	115648874	115087613	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	169203733	24715	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	169203733	166599121	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	115648874	1144	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	169203733	25859	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	115648874	24696	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	115648874	24715	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	169203733	24715	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	169203733	281288	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	115648874	115087613	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	169203733	30777	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	169203733	166599121	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	169203733	30775	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	115648874	30788	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	115648874	30780	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	169203733	30825	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	115648874	115087613	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	169203733	46	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	115648874	46	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	115648874	115087613	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	169203733	37	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	115648874	37	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	169203733	93776	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.DstReqKnown_A	0	0	460199019	455678244	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	169203733	24715	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	169203733	166599121	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	460199019	1144	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	169203733	25859	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	460199019	24715	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	460199019	24715	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	169203733	24715	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	169203733	117542	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	460199019	455678244	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	169203733	30627	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	169203733	166599121	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	169203733	30626	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	460199019	30635	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	460199019	30633	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	169203733	30646	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	460199019	455678244	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	169203733	33	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	460199019	33	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	460199019	455678244	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	169203733	33	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	460199019	33	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	169203733	91924	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.DstReqKnown_A	0	0	490035738	485259080	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	169203733	24715	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	169203733	166599121	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	490035738	1144	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	169203733	25859	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	490035738	24715	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	490035738	24715	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	169203733	24715	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	169203733	115590	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	490035738	485259080	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	169203733	30801	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	169203733	166599121	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	169203733	30797	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	490035738	30815	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	490035738	30811	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	169203733	30828	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	490035738	485259080	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	169203733	30	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	490035738	30	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	490035738	485259080	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	169203733	34	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	490035738	34	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	169203733	133560	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.DstReqKnown_A	0	0	235343874	233054064	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	169203733	24218	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	169203733	166599121	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	235343874	1144	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	169203733	25362	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	235343874	24149	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	235343874	24240	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	169203733	24715	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	169203733	170997	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	235343874	233054064	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	169203733	30559	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	169203733	166599121	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	169203733	30521	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	235343874	30739	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	235343874	30689	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	169203733	30863	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	235343874	233054064	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	169203733	30	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	235343874	30	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	235343874	233054064	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	169203733	31	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	235343874	31	0	0
tb.dut.u_reg.wePulse	0	0	169203733	666540	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	168225665	165719583	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_usb_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	168225665	2721	0	0
tb.dut.u_usb_meas.u_err_sync.SyncReqAckHoldReq	0	0	233936852	2721	0	0
tb.dut.u_usb_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	233936852	3888556	0	0
tb.dut.u_usb_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	233936852	109565	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	17501586	108801	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	233936852	232830542	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	233936852	232830542	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	168225665	25054874	0	58
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	168225665	165501914	0	2415
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	487104382	482514370	0	2415
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	487104382	482514370	0	2415
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	487104382	482514370	0	2415
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	487104382	482514370	0	2415
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	457385032	453043186	0	2415
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	231299016	0	0	1010
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	115648874	0	0	1010
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	460199019	0	0	1010
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	490035738	0	0	1010
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	235343874	0	0	1010
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	168225665	165712695	0	2415

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	169204353	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	169204353	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	169204353	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	169204353	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	169204353	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	169204353	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	169204353	6283	6283	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	169204353	3805	3805	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	169204353	13591	13591	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	169204353	94497	94497	755

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	169204353	6283	6283	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	169204353	3805	3805	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	169204353	13591	13591	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	169204353	94497	94497	755