Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	566052	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3315072

1

T5

196

T7

3

T8

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	958972	1			T5	16		T7	2		T8	12
values[0x0]	1345108	1			T5	186		T7	2		T8	10
values[0x1]	1577044	1			T5	182		T7	3		T8	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	311732	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3569392

1

T5

256

T7

4

T8

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14959	1			T1	1		T2	575		T68	3
valid_sources[0x01]	13879	1			T1	6		T2	557		T3	5
valid_sources[0x02]	15528	1			T1	7		T2	584		T24	1
valid_sources[0x03]	14321	1			T1	1		T2	568		T67	2
valid_sources[0x04]	14724	1			T8	1		T1	6		T2	594
valid_sources[0x05]	15372	1			T1	4		T2	550		T25	1
valid_sources[0x06]	16271	1			T1	3		T2	570		T67	2
valid_sources[0x07]	14298	1			T2	576		T24	2		T4	1
valid_sources[0x08]	15988	1			T1	15		T2	555		T25	1
valid_sources[0x09]	15593	1			T1	3		T2	603		T68	1
valid_sources[0x0a]	14045	1			T8	1		T1	8		T2	596
valid_sources[0x0b]	14707	1			T1	14		T2	521		T24	1
valid_sources[0x0c]	13603	1			T1	1		T2	555		T68	1
valid_sources[0x0d]	15935	1			T1	17		T2	524		T4	1
valid_sources[0x0e]	16029	1			T1	31		T2	542		T67	2
valid_sources[0x0f]	14196	1			T1	26		T2	573		T3	1
valid_sources[0x10]	15901	1			T1	13		T2	575		T24	1
valid_sources[0x11]	14678	1			T1	3		T2	589		T25	1
valid_sources[0x12]	14718	1			T1	11		T2	604		T67	2
valid_sources[0x13]	14735	1			T5	4		T1	13		T2	521
valid_sources[0x14]	14847	1			T1	5		T2	555		T25	1
valid_sources[0x15]	15476	1			T2	586		T4	2		T3	2
valid_sources[0x16]	15237	1			T1	11		T2	614		T3	1
valid_sources[0x17]	14442	1			T1	10		T2	556		T4	3
valid_sources[0x18]	15475	1			T1	23		T2	531		T12	8
valid_sources[0x19]	15653	1			T1	11		T2	571		T25	1
valid_sources[0x1a]	14093	1			T1	2		T2	574		T12	8
valid_sources[0x1b]	15854	1			T1	23		T2	570		T25	3
valid_sources[0x1c]	14358	1			T1	6		T6	1		T2	556
valid_sources[0x1d]	15171	1			T1	17		T2	573		T71	1
valid_sources[0x1e]	15517	1			T2	591		T3	3		T12	42
valid_sources[0x1f]	14026	1			T1	1		T2	546		T24	2
valid_sources[0x20]	15207	1			T1	2		T2	564		T70	4
valid_sources[0x21]	14523	1			T1	17		T2	555		T4	3
valid_sources[0x22]	15133	1			T1	5		T2	527		T25	1
valid_sources[0x23]	14028	1			T1	2		T2	597		T68	1
valid_sources[0x24]	15451	1			T1	4		T2	586		T25	3
valid_sources[0x25]	14486	1			T1	17		T2	608		T12	164
valid_sources[0x26]	15977	1			T1	3		T2	578		T4	2
valid_sources[0x27]	15388	1			T1	8		T2	554		T68	1
valid_sources[0x28]	13273	1			T8	1		T1	7		T2	589
valid_sources[0x29]	16445	1			T1	16		T6	5		T2	544
valid_sources[0x2a]	14660	1			T1	15		T2	587		T25	1
valid_sources[0x2b]	14532	1			T1	4		T2	689		T25	1
valid_sources[0x2c]	15046	1			T1	18		T2	578		T67	5
valid_sources[0x2d]	16030	1			T1	14		T2	591		T3	2
valid_sources[0x2e]	16346	1			T1	6		T2	612		T4	4
valid_sources[0x2f]	14599	1			T1	16		T2	586		T67	3
valid_sources[0x30]	15943	1			T1	15		T2	562		T68	2
valid_sources[0x31]	16153	1			T1	1		T2	600		T68	1
valid_sources[0x32]	14873	1			T1	3		T2	644		T24	1
valid_sources[0x33]	14899	1			T1	19		T2	571		T71	1
valid_sources[0x34]	14886	1			T8	2		T1	14		T2	579
valid_sources[0x35]	15621	1			T1	25		T2	617		T25	2
valid_sources[0x36]	17192	1			T1	16		T2	555		T25	2
valid_sources[0x37]	15197	1			T1	4		T2	594		T67	2
valid_sources[0x38]	15592	1			T1	14		T2	581		T24	1
valid_sources[0x39]	15497	1			T1	21		T2	568		T25	1
valid_sources[0x3a]	15830	1			T1	37		T21	37		T2	565
valid_sources[0x3b]	15314	1			T1	17		T2	550		T24	1
valid_sources[0x3c]	15709	1			T8	1		T1	21		T2	538
valid_sources[0x3d]	13993	1			T1	6		T6	1		T2	595
valid_sources[0x3e]	17341	1			T1	16		T2	572		T68	1
valid_sources[0x3f]	13951	1			T1	28		T2	530		T3	2
valid_sources[0x40]	14843	1			T1	14		T2	522		T4	6
valid_sources[0x41]	13856	1			T1	12		T2	584		T68	1
valid_sources[0x42]	14712	1			T1	11		T2	602		T12	47
valid_sources[0x43]	15307	1			T8	2		T1	28		T2	540
valid_sources[0x44]	15110	1			T1	19		T2	542		T24	1
valid_sources[0x45]	15925	1			T8	1		T1	17		T2	589
valid_sources[0x46]	14498	1			T8	1		T1	16		T2	570
valid_sources[0x47]	15055	1			T1	18		T2	595		T68	1
valid_sources[0x48]	14917	1			T5	73		T1	1		T2	541
valid_sources[0x49]	14834	1			T2	587		T24	1		T12	17
valid_sources[0x4a]	16019	1			T1	16		T6	5		T2	557
valid_sources[0x4b]	14398	1			T1	18		T2	561		T4	9
valid_sources[0x4c]	15455	1			T1	14		T2	555		T4	2
valid_sources[0x4d]	13821	1			T1	12		T2	563		T4	3
valid_sources[0x4e]	15852	1			T1	1		T2	617		T68	1
valid_sources[0x4f]	15899	1			T1	14		T2	547		T24	1
valid_sources[0x50]	15046	1			T1	10		T2	588		T25	1
valid_sources[0x51]	14925	1			T1	14		T2	579		T24	2
valid_sources[0x52]	16507	1			T1	11		T2	519		T68	1
valid_sources[0x53]	15310	1			T1	12		T2	544		T25	1
valid_sources[0x54]	14335	1			T2	591		T25	2		T4	3
valid_sources[0x55]	15177	1			T1	4		T2	571		T4	2
valid_sources[0x56]	14107	1			T5	8		T1	6		T2	557
valid_sources[0x57]	15563	1			T8	1		T1	1		T2	581
valid_sources[0x58]	14336	1			T8	2		T1	7		T2	554
valid_sources[0x59]	13983	1			T1	1		T2	540		T24	2
valid_sources[0x5a]	15452	1			T1	10		T2	578		T3	1
valid_sources[0x5b]	15771	1			T1	11		T2	533		T24	1
valid_sources[0x5c]	14049	1			T1	18		T2	555		T25	1
valid_sources[0x5d]	15882	1			T1	17		T2	556		T4	6
valid_sources[0x5e]	15918	1			T1	3		T2	509		T12	22
valid_sources[0x5f]	14630	1			T1	5		T2	606		T25	1
valid_sources[0x60]	15156	1			T1	16		T2	577		T25	1
valid_sources[0x61]	14655	1			T1	10		T2	594		T12	153
valid_sources[0x62]	15122	1			T1	7		T2	557		T71	1
valid_sources[0x63]	16259	1			T1	2		T2	546		T69	6
valid_sources[0x64]	14675	1			T1	1		T2	577		T24	1
valid_sources[0x65]	14661	1			T1	2		T2	598		T25	3
valid_sources[0x66]	14726	1			T1	11		T2	589		T25	2
valid_sources[0x67]	14515	1			T1	6		T2	579		T25	1
valid_sources[0x68]	15039	1			T2	604		T24	1		T25	4
valid_sources[0x69]	14724	1			T2	571		T68	2		T12	379
valid_sources[0x6a]	16921	1			T1	17		T2	585		T68	1
valid_sources[0x6b]	15420	1			T1	10		T2	560		T4	2
valid_sources[0x6c]	13459	1			T1	2		T2	546		T4	1
valid_sources[0x6d]	15641	1			T2	533		T25	2		T12	150
valid_sources[0x6e]	17506	1			T1	6		T2	584		T68	1
valid_sources[0x6f]	14886	1			T8	2		T1	4		T2	552
valid_sources[0x70]	15409	1			T1	14		T2	618		T4	9
valid_sources[0x71]	15329	1			T1	19		T2	515		T67	1
valid_sources[0x72]	15554	1			T8	2		T1	1		T2	603
valid_sources[0x73]	13819	1			T1	5		T2	547		T25	3
valid_sources[0x74]	16175	1			T1	13		T2	548		T25	1
valid_sources[0x75]	15781	1			T8	2		T1	5		T2	549
valid_sources[0x76]	15498	1			T1	11		T2	547		T12	8
valid_sources[0x77]	14177	1			T1	7		T2	540		T24	1
valid_sources[0x78]	14828	1			T1	10		T2	535		T71	1
valid_sources[0x79]	15338	1			T8	1		T1	5		T23	31
valid_sources[0x7a]	14312	1			T1	19		T2	608		T24	7
valid_sources[0x7b]	14432	1			T1	11		T2	589		T25	1
valid_sources[0x7c]	15117	1			T1	4		T2	538		T25	1
valid_sources[0x7d]	14971	1			T2	605		T4	9		T12	142
valid_sources[0x7e]	15747	1			T1	2		T2	555		T4	2
valid_sources[0x7f]	14189	1			T1	5		T2	550		T24	1
valid_sources[0x80]	14580	1			T1	4		T2	595		T24	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

838941

1

T5

4

T7

1

T8

4

values[0x0]

all_enables

biggest_size

1259538

1

T5

126

T7

1

T8

3

values[0x1]

all_enables

biggest_size

1216593

1

T5

66

T7

1

T8

2