Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_trans_cg_wrap::trans_cg

Group : clkmgr_env_pkg::clkmgr_trans_cg_wrap::trans_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
TransAes	100.00	1	100	1	64	64
TransHmac	100.00	1	100	1	64	64
TransKmac	100.00	1	100	1	64	64
TransOtbn	100.00	1	100	1	64	64

---

Group Instance : TransAes

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransAes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransAes

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransAes

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransHmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransHmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransHmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransHmac

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransKmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransKmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransKmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransKmac

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransOtbn

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransOtbn

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransOtbn

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransOtbn

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1270990

1

T5

6

T7

2

T8

2

auto[1]

442700155

1

T5

153233

T7

3667

T8

1975

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

408940370

1

T5

151364

T7

90

T8

1397

auto[1]

35030775

1

T5

1875

T7

3579

T8

580

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10869

1

T5

6

T7

2

T8

2

auto[1]

443960276

1

T5

153233

T7

3667

T8

1975

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

217431880

1

T5

153055

T7

3669

T8

1846

auto[1]

226539265

1

T5

184

T8

131

T1

544154

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2454

1

T12

4

T63

2

T64

2

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T62

2

T63

4

T134

2

auto[0]

auto[1]

auto[0]

auto[0]

426618

1

T1

7506

T2

31429

T68

678

auto[0]

auto[1]

auto[0]

auto[1]

366126

1

T1

774

T2

6758

T68

282

auto[0]

auto[1]

auto[1]

auto[0]

391663

1

T1

5344

T2

35105

T25

416

auto[0]

auto[1]

auto[1]

auto[1]

79923

1

T1

2126

T2

8166

T68

470

auto[1]

auto[1]

auto[0]

auto[0]

199100165

1

T5

151302

T7

88

T8

1387

auto[1]

auto[1]

auto[0]

auto[1]

17529622

1

T5

1751

T7

3579

T8

459

auto[1]

auto[1]

auto[1]

auto[0]

209015507

1

T5

56

T8

8

T1

523374

auto[1]

auto[1]

auto[1]

auto[1]

17050652

1

T5

124

T8

121

T1

13298

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1265667

1

T5

6

T7

2

T8

2

auto[1]

442705478

1

T5

153233

T7

3667

T8

1975

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

376123589

1

T5

153135

T7

3669

T8

1589

auto[1]

67847556

1

T5

104

T8

388

T1

36640

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10869

1

T5

6

T7

2

T8

2

auto[1]

443960276

1

T5

153233

T7

3667

T8

1975

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

217431880

1

T5

153055

T7

3669

T8

1846

auto[1]

226539265

1

T5

184

T8

131

T1

544154

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2460

1

T12

2

T14

2

T15

2

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T2

2

T14

2

T62

2

auto[0]

auto[1]

auto[0]

auto[0]

394417

1

T1

6904

T2

30933

T68

388

auto[0]

auto[1]

auto[0]

auto[1]

407499

1

T1

1966

T2

7776

T68

188

auto[0]

auto[1]

auto[1]

auto[0]

377893

1

T1

5996

T2

36666

T25

314

auto[0]

auto[1]

auto[1]

auto[1]

79198

1

T1

804

T2

8169

T68

282

auto[1]

auto[1]

auto[0]

auto[0]

183945158

1

T5

152991

T7

3667

T8

1458

auto[1]

auto[1]

auto[0]

auto[1]

32675457

1

T5

62

T8

388

T1

28994

auto[1]

auto[1]

auto[1]

auto[0]

191399444

1

T5

138

T8

129

T1

532466

auto[1]

auto[1]

auto[1]

auto[1]

34681210

1

T5

42

T1

4876

T22

544

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1073007

1

T5

6

T7

2

T8

2

auto[1]

442898138

1

T5

153233

T7

3667

T8

1975

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

381598736

1

T5

153052

T7

90

T8

1549

auto[1]

62372409

1

T5

187

T7

3579

T8

428

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10869

1

T5

6

T7

2

T8

2

auto[1]

443960276

1

T5

153233

T7

3667

T8

1975

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

217431880

1

T5

153055

T7

3669

T8

1846

auto[1]

226539265

1

T5

184

T8

131

T1

544154

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2458

1

T2

2

T14

2

T15

2

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T2

2

T63

2

T152

2

auto[0]

auto[1]

auto[0]

auto[0]

339356

1

T1

7580

T2

25560

T68

388

auto[0]

auto[1]

auto[0]

auto[1]

322226

1

T1

1390

T2

7839

T68

188

auto[0]

auto[1]

auto[1]

auto[0]

326151

1

T1

4014

T2

24408

T25

198

auto[0]

auto[1]

auto[1]

auto[1]

78614

1

T1

626

T2

6490

T71

51

auto[1]

auto[1]

auto[0]

auto[0]

189639170

1

T5

153012

T7

88

T8

1491

auto[1]

auto[1]

auto[0]

auto[1]

27121779

1

T5

41

T7

3579

T8

355

auto[1]

auto[1]

auto[1]

auto[0]

191287908

1

T5

34

T8

56

T1

524910

auto[1]

auto[1]

auto[1]

auto[1]

34845072

1

T5

146

T8

73

T1

14592

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051502

1

T5

6

T7

2

T8

2

auto[1]

442919643

1

T5

153233

T7

3667

T8

1975

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

389846753

1

T5

151425

T7

90

T8

495

auto[1]

54124392

1

T5

1814

T7

3579

T8

1482

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10869

1

T5

6

T7

2

T8

2

auto[1]

443960276

1

T5

153233

T7

3667

T8

1975

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

217431880

1

T5

153055

T7

3669

T8

1846

auto[1]

226539265

1

T5

184

T8

131

T1

544154

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2464

1

T12

2

T14

2

T15

2

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T2

2

T14

2

T63

4

auto[0]

auto[1]

auto[0]

auto[0]

283173

1

T1

4828

T2

25684

T68

584

auto[0]

auto[1]

auto[0]

auto[1]

386577

1

T1

1042

T2

7515

T68

376

auto[0]

auto[1]

auto[1]

auto[0]

296795

1

T1

6586

T2

25996

T25

110

auto[0]

auto[1]

auto[1]

auto[1]

78297

1

T1

844

T2

8864

T68

188

auto[1]

auto[1]

auto[0]

auto[0]

199571229

1

T5

151343

T7

88

T8

437

auto[1]

auto[1]

auto[0]

auto[1]

17181552

1

T5

1710

T7

3579

T8

1409

auto[1]

auto[1]

auto[1]

auto[0]

189689151

1

T5

76

T8

56

T1

531516

auto[1]

auto[1]

auto[1]

auto[1]

36473502

1

T5

104

T8

73

T1

5196

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded