Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T37,T38,T39
1	1	Covered	T5,T7,T8

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	946141280	13206	0	0
GateOpen_A	946141280	19344	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946141280	13206	0	0
T1	2143296	49	0	0
T2	0	417	0	0
T5	373832	32	0	0
T6	57058	0	0	0
T7	8342	0	0	0
T8	4780	0	0	0
T12	0	248	0	0
T13	0	91	0	0
T14	0	122	0	0
T15	0	259	0	0
T17	0	57	0	0
T19	11145	0	0	0
T20	4925	0	0	0
T21	5417	0	0	0
T22	19200	0	0	0
T23	13150	0	0	0
T25	0	39	0	0
T37	0	11	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946141280	19344	0	0
T1	2143296	57	0	0
T2	0	433	0	0
T4	0	28	0	0
T5	373832	36	0	0
T6	57058	0	0	0
T7	8342	4	0	0
T8	4780	0	0	0
T19	11145	0	0	0
T20	4925	0	0	0
T21	5417	0	0	0
T22	19200	4	0	0
T23	13150	0	0	0
T25	0	39	0	0
T26	0	80	0	0
T68	0	4	0	0
T69	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T37,T38,T39
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	104324518	3152	0	0
GateOpen_A	104324518	4685	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104324518	3152	0	0
T1	233201	13	0	0
T2	0	112	0	0
T5	41176	10	0	0
T6	6329	0	0	0
T7	938	0	0	0
T8	535	0	0	0
T12	0	60	0	0
T13	0	21	0	0
T14	0	32	0	0
T15	0	64	0	0
T17	0	15	0	0
T19	1243	0	0	0
T20	535	0	0	0
T21	625	0	0	0
T22	2287	0	0	0
T23	1563	0	0	0
T25	0	8	0	0
T37	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104324518	4685	0	0
T1	233201	15	0	0
T2	0	116	0	0
T4	0	7	0	0
T5	41176	11	0	0
T6	6329	0	0	0
T7	938	1	0	0
T8	535	0	0	0
T19	1243	0	0	0
T20	535	0	0	0
T21	625	0	0	0
T22	2287	1	0	0
T23	1563	0	0	0
T25	0	8	0	0
T26	0	20	0	0
T68	0	1	0	0
T69	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T37,T38,T39
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	208649658	3376	0	0
GateOpen_A	208649658	4909	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208649658	3376	0	0
T1	466402	12	0	0
T2	0	103	0	0
T5	82352	6	0	0
T6	12658	0	0	0
T7	1876	0	0	0
T8	1072	0	0	0
T12	0	63	0	0
T13	0	25	0	0
T14	0	31	0	0
T15	0	65	0	0
T17	0	14	0	0
T19	2486	0	0	0
T20	1071	0	0	0
T21	1250	0	0	0
T22	4577	0	0	0
T23	3127	0	0	0
T25	0	11	0	0
T37	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208649658	4909	0	0
T1	466402	14	0	0
T2	0	107	0	0
T4	0	7	0	0
T5	82352	7	0	0
T6	12658	0	0	0
T7	1876	1	0	0
T8	1072	0	0	0
T19	2486	0	0	0
T20	1071	0	0	0
T21	1250	0	0	0
T22	4577	1	0	0
T23	3127	0	0	0
T25	0	11	0	0
T26	0	20	0	0
T68	0	1	0	0
T69	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T37,T38,T39
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	418836812	3331	0	0
GateOpen_A	418836812	4867	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418836812	3331	0	0
T1	929807	14	0	0
T2	0	99	0	0
T5	164947	7	0	0
T6	25380	0	0	0
T7	3685	0	0	0
T8	2115	0	0	0
T12	0	60	0	0
T13	0	23	0	0
T14	0	31	0	0
T15	0	65	0	0
T17	0	12	0	0
T19	4944	0	0	0
T20	2213	0	0	0
T21	2361	0	0	0
T22	8224	0	0	0
T23	5640	0	0	0
T25	0	11	0	0
T37	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418836812	4867	0	0
T1	929807	16	0	0
T2	0	103	0	0
T4	0	7	0	0
T5	164947	8	0	0
T6	25380	0	0	0
T7	3685	1	0	0
T8	2115	0	0	0
T19	4944	0	0	0
T20	2213	0	0	0
T21	2361	0	0	0
T22	8224	1	0	0
T23	5640	0	0	0
T25	0	11	0	0
T26	0	20	0	0
T68	0	1	0	0
T69	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T37,T38,T39
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	214330292	3347	0	0
GateOpen_A	214330292	4883	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214330292	3347	0	0
T1	513886	10	0	0
T2	0	103	0	0
T5	85357	9	0	0
T6	12691	0	0	0
T7	1843	0	0	0
T8	1058	0	0	0
T12	0	65	0	0
T13	0	22	0	0
T14	0	28	0	0
T15	0	65	0	0
T17	0	16	0	0
T19	2472	0	0	0
T20	1106	0	0	0
T21	1181	0	0	0
T22	4112	0	0	0
T23	2820	0	0	0
T25	0	9	0	0
T37	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214330292	4883	0	0
T1	513886	12	0	0
T2	0	107	0	0
T4	0	7	0	0
T5	85357	10	0	0
T6	12691	0	0	0
T7	1843	1	0	0
T8	1058	0	0	0
T19	2472	0	0	0
T20	1106	0	0	0
T21	1181	0	0	0
T22	4112	1	0	0
T23	2820	0	0	0
T25	0	9	0	0
T26	0	20	0	0
T68	0	1	0	0
T69	0	1	0	0