Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	728428915	67986	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	728428915	67986	0	0
T1	556285	381	0	0
T2	1978505	1008	0	0
T3	0	150	0	0
T6	62125	0	0	0
T12	0	297	0	0
T13	0	902	0	0
T14	0	559	0	0
T15	0	2896	0	0
T16	0	49	0	0
T17	0	178	0	0
T18	0	284	0	0
T19	4630	0	0	0
T20	5650	0	0	0
T21	12055	0	0	0
T22	10705	0	0	0
T23	8515	0	0	0
T24	48170	0	0	0
T25	16980	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145685783	10014	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145685783	10014	0	0
T1	111257	72	0	0
T2	395701	193	0	0
T3	0	25	0	0
T6	12425	0	0	0
T12	0	44	0	0
T13	0	115	0	0
T14	0	98	0	0
T15	0	374	0	0
T16	0	7	0	0
T17	0	29	0	0
T18	0	46	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	9634	0	0	0
T25	3396	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145685783	13639	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145685783	13639	0	0
T1	111257	75	0	0
T2	395701	193	0	0
T3	0	30	0	0
T6	12425	0	0	0
T12	0	60	0	0
T13	0	181	0	0
T14	0	110	0	0
T15	0	579	0	0
T16	0	10	0	0
T17	0	36	0	0
T18	0	58	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	9634	0	0	0
T25	3396	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145685783	20726	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145685783	20726	0	0
T1	111257	90	0	0
T2	395701	236	0	0
T3	0	41	0	0
T6	12425	0	0	0
T12	0	97	0	0
T13	0	296	0	0
T14	0	140	0	0
T15	0	950	0	0
T16	0	15	0	0
T17	0	49	0	0
T18	0	77	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	9634	0	0	0
T25	3396	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145685783	9861	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145685783	9861	0	0
T1	111257	72	0	0
T2	395701	193	0	0
T3	0	24	0	0
T6	12425	0	0	0
T12	0	38	0	0
T13	0	130	0	0
T14	0	98	0	0
T15	0	422	0	0
T16	0	8	0	0
T17	0	28	0	0
T18	0	45	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	9634	0	0	0
T25	3396	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145685783	13746	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145685783	13746	0	0
T1	111257	72	0	0
T2	395701	193	0	0
T3	0	30	0	0
T6	12425	0	0	0
T12	0	58	0	0
T13	0	180	0	0
T14	0	113	0	0
T15	0	571	0	0
T16	0	9	0	0
T17	0	36	0	0
T18	0	58	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	9634	0	0	0
T25	3396	0	0	0