Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	145685783	143216510	0	0
AllClkBypReqTrue_A	145685783	113769	0	0
IoClkBypReqFalse_A	145685783	143147290	0	2415
IoClkBypReqTrue_A	145685783	178623	0	0
LcClkBypAckFalse_A	145685783	143226993	0	0
LcClkBypAckTrue_A	145685783	103286	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145685783	143216510	0	0
T1	111257	110717	0	0
T5	195822	195236	0	0
T6	12425	12325	0	0
T7	920	855	0	0
T8	2138	1888	0	0
T19	926	903	0	0
T20	1130	1028	0	0
T21	2411	1967	0	0
T22	2141	1833	0	0
T23	1703	1452	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145685783	113769	0	0
T1	111257	403	0	0
T2	395701	1104	0	0
T6	12425	0	0	0
T7	920	24	0	0
T8	2138	29	0	0
T19	926	0	0	0
T20	1130	18	0	0
T21	2411	221	0	0
T22	2141	279	0	0
T23	1703	176	0	0
T67	0	66	0	0
T69	0	108	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145685783	143147290	0	2415
T1	111257	110589	0	3
T5	195822	195230	0	3
T6	12425	12323	0	3
T7	920	849	0	3
T8	2138	1582	0	3
T19	926	857	0	3
T20	1130	1044	0	3
T21	2411	1789	0	3
T22	2141	1767	0	3
T23	1703	1353	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145685783	178623	0	0
T1	111257	515	0	0
T2	395701	1786	0	0
T6	12425	0	0	0
T7	920	28	0	0
T8	2138	333	0	0
T19	926	44	0	0
T20	1130	0	0	0
T21	2411	397	0	0
T22	2141	343	0	0
T23	1703	273	0	0
T67	0	74	0	0
T69	0	224	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145685783	143226993	0	0
T1	111257	110835	0	0
T5	195822	195236	0	0
T6	12425	12325	0	0
T7	920	855	0	0
T8	2138	1796	0	0
T19	926	896	0	0
T20	1130	1046	0	0
T21	2411	1974	0	0
T22	2141	1934	0	0
T23	1703	1423	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145685783	103286	0	0
T1	111257	285	0	0
T2	395701	1039	0	0
T6	12425	0	0	0
T7	920	24	0	0
T8	2138	121	0	0
T19	926	7	0	0
T20	1130	0	0	0
T21	2411	214	0	0
T22	2141	178	0	0
T23	1703	205	0	0
T67	0	40	0	0
T69	0	94	0	0