Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1783963140	14779	0	0
TransStop_A	1783963140	7562	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1783963140	14779	0	0
T1	430632	85	0	0
T2	1972504	451	0	0
T6	81756	0	0	0
T12	0	73	0	0
T13	0	82	0	0
T14	0	339	0	0
T15	0	96	0	0
T19	20600	0	0	0
T20	9224	0	0	0
T21	9840	0	0	0
T22	34268	0	0	0
T23	23504	0	0	0
T24	136580	0	0	0
T25	27176	4	0	0
T68	0	31	0	0
T70	0	10	0	0
T71	0	25	0	0
T106	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1783963140	7562	0	0
T1	430632	46	0	0
T2	1972504	217	0	0
T6	81756	0	0	0
T12	0	49	0	0
T13	0	56	0	0
T14	0	158	0	0
T15	0	205	0	0
T19	20600	0	0	0
T20	9224	0	0	0
T21	9840	0	0	0
T22	34268	0	0	0
T23	23504	0	0	0
T24	136580	0	0	0
T25	27176	0	0	0
T68	0	16	0	0
T70	0	6	0	0
T71	0	7	0	0
T106	0	2	0	0
T107	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	445990785	3717	0	0
TransStop_A	445990785	1897	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990785	3717	0	0
T1	107658	20	0	0
T2	493126	113	0	0
T6	20439	0	0	0
T12	0	19	0	0
T13	0	20	0	0
T14	0	82	0	0
T19	5150	0	0	0
T20	2306	0	0	0
T21	2460	0	0	0
T22	8567	0	0	0
T23	5876	0	0	0
T24	34145	0	0	0
T25	6794	1	0	0
T68	0	10	0	0
T70	0	2	0	0
T71	0	7	0	0
T106	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990785	1897	0	0
T1	107658	10	0	0
T2	493126	53	0	0
T6	20439	0	0	0
T12	0	14	0	0
T13	0	13	0	0
T14	0	42	0	0
T15	0	51	0	0
T19	5150	0	0	0
T20	2306	0	0	0
T21	2460	0	0	0
T22	8567	0	0	0
T23	5876	0	0	0
T24	34145	0	0	0
T25	6794	0	0	0
T68	0	5	0	0
T70	0	1	0	0
T71	0	3	0	0
T106	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	445990785	3752	0	0
TransStop_A	445990785	1923	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990785	3752	0	0
T1	107658	22	0	0
T2	493126	122	0	0
T6	20439	0	0	0
T12	0	17	0	0
T13	0	19	0	0
T14	0	87	0	0
T19	5150	0	0	0
T20	2306	0	0	0
T21	2460	0	0	0
T22	8567	0	0	0
T23	5876	0	0	0
T24	34145	0	0	0
T25	6794	1	0	0
T68	0	9	0	0
T70	0	4	0	0
T71	0	5	0	0
T106	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990785	1923	0	0
T1	107658	12	0	0
T2	493126	56	0	0
T6	20439	0	0	0
T12	0	12	0	0
T13	0	12	0	0
T14	0	47	0	0
T15	0	51	0	0
T19	5150	0	0	0
T20	2306	0	0	0
T21	2460	0	0	0
T22	8567	0	0	0
T23	5876	0	0	0
T24	34145	0	0	0
T25	6794	0	0	0
T68	0	3	0	0
T70	0	2	0	0
T71	0	1	0	0
T106	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	445990785	3666	0	0
TransStop_A	445990785	1889	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990785	3666	0	0
T1	107658	21	0	0
T2	493126	102	0	0
T6	20439	0	0	0
T12	0	19	0	0
T13	0	22	0	0
T14	0	87	0	0
T15	0	96	0	0
T19	5150	0	0	0
T20	2306	0	0	0
T21	2460	0	0	0
T22	8567	0	0	0
T23	5876	0	0	0
T24	34145	0	0	0
T25	6794	1	0	0
T68	0	5	0	0
T70	0	1	0	0
T71	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990785	1889	0	0
T1	107658	14	0	0
T2	493126	53	0	0
T6	20439	0	0	0
T12	0	12	0	0
T13	0	16	0	0
T14	0	34	0	0
T15	0	49	0	0
T19	5150	0	0	0
T20	2306	0	0	0
T21	2460	0	0	0
T22	8567	0	0	0
T23	5876	0	0	0
T24	34145	0	0	0
T25	6794	0	0	0
T68	0	3	0	0
T70	0	1	0	0
T71	0	2	0	0
T107	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	445990785	3644	0	0
TransStop_A	445990785	1853	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990785	3644	0	0
T1	107658	22	0	0
T2	493126	114	0	0
T6	20439	0	0	0
T12	0	18	0	0
T13	0	21	0	0
T14	0	83	0	0
T19	5150	0	0	0
T20	2306	0	0	0
T21	2460	0	0	0
T22	8567	0	0	0
T23	5876	0	0	0
T24	34145	0	0	0
T25	6794	1	0	0
T68	0	7	0	0
T70	0	3	0	0
T71	0	7	0	0
T106	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990785	1853	0	0
T1	107658	10	0	0
T2	493126	55	0	0
T6	20439	0	0	0
T12	0	11	0	0
T13	0	15	0	0
T14	0	35	0	0
T15	0	54	0	0
T19	5150	0	0	0
T20	2306	0	0	0
T21	2460	0	0	0
T22	8567	0	0	0
T23	5876	0	0	0
T24	34145	0	0	0
T25	6794	0	0	0
T68	0	5	0	0
T70	0	2	0	0
T71	0	1	0	0
T107	0	3	0	0