Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	145685783	17904977	0	59

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145685783	17904977	0	59
T1	111257	15526	0	0
T2	395701	441589	0	0
T3	0	9976	0	1
T6	12425	0	0	0
T12	0	36895	0	0
T13	0	571028	0	0
T14	0	143711	0	0
T15	0	324357	0	0
T16	0	5606	0	1
T17	0	14402	0	0
T18	0	0	0	1
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	9634	0	0	0
T25	3396	0	0	0
T27	0	0	0	1
T28	0	0	0	1
T30	0	952	0	1
T31	0	0	0	1
T108	0	0	0	1
T109	0	0	0	1
T110	0	0	0	1