Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	146591435	4807829	0	0
clk_enables_rd_A	146591435	49549	0	0
clk_hints_rd_A	146591435	46849	0	0
extclk_ctrl_rd_A	146591435	59596	0	0
extclk_ctrl_regwen_rd_A	146591435	45098	0	0
jitter_enable_rd_A	146591435	63800	0	0
jitter_regwen_rd_A	146591435	49753	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	4807829	0	0
T2	395701	192821	0	0
T4	49162	0	0	0
T12	0	31856	0	0
T13	0	56080	0	0
T14	0	151089	0	0
T15	0	126509	0	0
T24	9634	0	0	0
T25	3396	0	0	0
T26	25814	0	0	0
T62	0	188746	0	0
T63	0	96902	0	0
T64	0	133514	0	0
T65	0	160889	0	0
T66	0	71671	0	0
T67	1881	0	0	0
T68	2172	0	0	0
T69	1643	0	0	0
T70	1779	0	0	0
T71	2814	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	49549	0	0
T4	49162	0	0	0
T12	0	1349	0	0
T13	0	1995	0	0
T15	0	4665	0	0
T17	0	9	0	0
T25	3396	4	0	0
T26	25814	0	0	0
T29	49923	0	0	0
T31	0	12	0	0
T63	0	3944	0	0
T67	1881	0	0	0
T68	2172	0	0	0
T69	1643	0	0	0
T70	1779	0	0	0
T71	2814	0	0	0
T130	0	7	0	0
T131	0	6	0	0
T132	0	1837	0	0
T133	851	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	46849	0	0
T4	49162	0	0	0
T12	0	1136	0	0
T13	0	1870	0	0
T15	0	4714	0	0
T17	0	14	0	0
T25	3396	5	0	0
T26	25814	0	0	0
T29	49923	0	0	0
T31	0	22	0	0
T63	0	3366	0	0
T67	1881	0	0	0
T68	2172	0	0	0
T69	1643	0	0	0
T70	1779	0	0	0
T71	2814	0	0	0
T131	0	3	0	0
T132	0	1784	0	0
T133	851	0	0	0
T134	0	1457	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	59596	0	0
T3	47764	0	0	0
T12	114595	1704	0	0
T13	0	2423	0	0
T15	0	5343	0	0
T17	0	78	0	0
T26	25814	0	0	0
T29	49923	0	0	0
T31	0	114	0	0
T37	1304	0	0	0
T69	1643	23	0	0
T70	1779	0	0	0
T71	2814	0	0	0
T72	0	97	0	0
T84	0	63	0	0
T85	0	29	0	0
T133	851	0	0	0
T135	1447	2	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	45098	0	0
T9	47228	0	0	0
T12	114595	1082	0	0
T13	195150	1898	0	0
T14	295432	0	0	0
T15	461353	4257	0	0
T32	1637	0	0	0
T42	0	4543	0	0
T63	0	3304	0	0
T72	98228	63	0	0
T98	21886	0	0	0
T106	1296	0	0	0
T111	1235	0	0	0
T132	0	1661	0	0
T134	0	1768	0	0
T136	0	37	0	0
T137	0	55	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	63800	0	0
T4	49162	0	0	0
T12	0	1346	0	0
T13	0	1999	0	0
T15	0	5927	0	0
T17	0	424	0	0
T25	3396	126	0	0
T26	25814	0	0	0
T29	49923	0	0	0
T31	0	438	0	0
T63	0	5191	0	0
T67	1881	0	0	0
T68	2172	0	0	0
T69	1643	0	0	0
T70	1779	0	0	0
T71	2814	0	0	0
T130	0	69	0	0
T131	0	208	0	0
T132	0	2290	0	0
T133	851	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	49753	0	0
T9	47228	0	0	0
T12	114595	1278	0	0
T13	195150	2155	0	0
T14	295432	0	0	0
T15	461353	4700	0	0
T32	1637	0	0	0
T42	0	4813	0	0
T63	0	3860	0	0
T72	98228	0	0	0
T98	21886	0	0	0
T106	1296	0	0	0
T111	1235	0	0	0
T132	0	2065	0	0
T134	0	1887	0	0
T138	0	2697	0	0
T139	0	1745	0	0
T140	0	595	0	0