Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T2,T4,T26
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1465914350	1300526	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1465914350	250547	0	0
SrcBusyKnown_A	1465914350	1441307080	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1465914350	1300526	0	0
T1	1112570	3834	0	0
T2	0	20033	0	0
T3	0	1128	0	0
T4	0	1578	0	0
T5	1958220	2756	0	0
T6	124250	217	0	0
T7	9200	0	0	0
T8	21380	0	0	0
T12	0	13503	0	0
T19	9260	0	0	0
T20	11300	0	0	0
T21	24110	0	0	0
T22	21410	0	0	0
T23	17030	0	0	0
T24	0	204	0	0
T26	0	1693	0	0
T29	0	1204	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4501902	4496790	0	0
T5	1055304	1051982	0	0
T6	154990	153750	0	0
T7	24356	23490	0	0
T8	13960	12692	0	0
T19	32582	31822	0	0
T20	14458	13552	0	0
T21	15748	14460	0	0
T22	55526	54920	0	0
T23	38048	36618	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1465914350	250547	0	0
T1	1112570	1380	0	0
T2	0	7750	0	0
T3	0	320	0	0
T4	0	199	0	0
T5	1958220	320	0	0
T6	124250	40	0	0
T7	9200	0	0	0
T8	21380	0	0	0
T12	0	1615	0	0
T19	9260	0	0	0
T20	11300	0	0	0
T21	24110	0	0	0
T22	21410	0	0	0
T23	17030	0	0	0
T24	0	60	0	0
T26	0	550	0	0
T29	0	340	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1465914350	1441307080	0	0
T1	1112570	1111280	0	0
T5	1958220	1952390	0	0
T6	124250	123260	0	0
T7	9200	8800	0	0
T8	21380	19180	0	0
T19	9260	9040	0	0
T20	11300	10470	0	0
T21	24110	21890	0	0
T22	21410	21130	0	0
T23	17030	16290	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146591435	79450	0	0
DstReqKnown_A	421156755	416910288	0	0
SrcAckBusyChk_A	146591435	22185	0	0
SrcBusyKnown_A	146591435	144130708	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	79450	0	0
T1	111257	359	0	0
T2	0	1918	0	0
T3	0	82	0	0
T4	0	70	0	0
T5	195822	168	0	0
T6	12425	15	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	942	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	15	0	0
T26	0	97	0	0
T29	0	89	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421156755	416910288	0	0
T1	929807	928534	0	0
T5	164947	164387	0	0
T6	25380	25177	0	0
T7	3685	3523	0	0
T8	2115	1898	0	0
T19	4943	4822	0	0
T20	2213	2051	0	0
T21	2361	2144	0	0
T22	8223	8116	0	0
T23	5640	5395	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	22185	0	0
T1	111257	138	0	0
T2	0	770	0	0
T3	0	32	0	0
T4	0	14	0	0
T5	195822	32	0	0
T6	12425	4	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	158	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	6	0	0
T26	0	38	0	0
T29	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	144130708	0	0
T1	111257	111128	0	0
T5	195822	195239	0	0
T6	12425	12326	0	0
T7	920	880	0	0
T8	2138	1918	0	0
T19	926	904	0	0
T20	1130	1047	0	0
T21	2411	2189	0	0
T22	2141	2113	0	0
T23	1703	1629	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146591435	113700	0	0
DstReqKnown_A	209762806	208680602	0	0
SrcAckBusyChk_A	146591435	22185	0	0
SrcBusyKnown_A	146591435	144130708	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	113700	0	0
T1	111257	359	0	0
T2	0	1918	0	0
T3	0	118	0	0
T4	0	113	0	0
T5	195822	281	0	0
T6	12425	22	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	1334	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	21	0	0
T26	0	118	0	0
T29	0	123	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209762806	208680602	0	0
T1	466402	466058	0	0
T5	82351	82193	0	0
T6	12657	12588	0	0
T7	1875	1861	0	0
T8	1071	1016	0	0
T19	2485	2437	0	0
T20	1070	1042	0	0
T21	1249	1187	0	0
T22	4577	4556	0	0
T23	3127	3065	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	22185	0	0
T1	111257	138	0	0
T2	0	770	0	0
T3	0	32	0	0
T4	0	14	0	0
T5	195822	32	0	0
T6	12425	4	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	158	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	6	0	0
T26	0	38	0	0
T29	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	144130708	0	0
T1	111257	111128	0	0
T5	195822	195239	0	0
T6	12425	12326	0	0
T7	920	880	0	0
T8	2138	1918	0	0
T19	926	904	0	0
T20	1130	1047	0	0
T21	2411	2189	0	0
T22	2141	2113	0	0
T23	1703	1629	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146591435	181260	0	0
DstReqKnown_A	104880891	104339908	0	0
SrcAckBusyChk_A	146591435	22185	0	0
SrcBusyKnown_A	146591435	144130708	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	181260	0	0
T1	111257	477	0	0
T2	0	2293	0	0
T3	0	167	0	0
T4	0	196	0	0
T5	195822	472	0	0
T6	12425	35	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	2289	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	30	0	0
T26	0	156	0	0
T29	0	178	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104880891	104339908	0	0
T1	233200	233029	0	0
T5	41176	41097	0	0
T6	6329	6295	0	0
T7	938	931	0	0
T8	534	506	0	0
T19	1242	1218	0	0
T20	535	521	0	0
T21	625	594	0	0
T22	2286	2276	0	0
T23	1562	1531	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	22185	0	0
T1	111257	138	0	0
T2	0	770	0	0
T3	0	32	0	0
T4	0	14	0	0
T5	195822	32	0	0
T6	12425	4	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	158	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	6	0	0
T26	0	38	0	0
T29	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	144130708	0	0
T1	111257	111128	0	0
T5	195822	195239	0	0
T6	12425	12326	0	0
T7	920	880	0	0
T8	2138	1918	0	0
T19	926	904	0	0
T20	1130	1047	0	0
T21	2411	2189	0	0
T22	2141	2113	0	0
T23	1703	1629	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146591435	77978	0	0
DstReqKnown_A	448407550	443971145	0	0
SrcAckBusyChk_A	146591435	22185	0	0
SrcBusyKnown_A	146591435	144130708	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	77978	0	0
T1	111257	359	0	0
T2	0	1918	0	0
T3	0	80	0	0
T4	0	69	0	0
T5	195822	196	0	0
T6	12425	15	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	765	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	15	0	0
T26	0	97	0	0
T29	0	89	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448407550	443971145	0	0
T1	107657	107525	0	0
T5	153822	153239	0	0
T6	20438	20226	0	0
T7	3838	3669	0	0
T8	2203	1977	0	0
T19	5149	5023	0	0
T20	2305	2136	0	0
T21	2459	2233	0	0
T22	8566	8454	0	0
T23	5875	5620	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	22185	0	0
T1	111257	138	0	0
T2	0	770	0	0
T3	0	32	0	0
T4	0	14	0	0
T5	195822	32	0	0
T6	12425	4	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	158	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	6	0	0
T26	0	38	0	0
T29	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	144130708	0	0
T1	111257	111128	0	0
T5	195822	195239	0	0
T6	12425	12326	0	0
T7	920	880	0	0
T8	2138	1918	0	0
T19	926	904	0	0
T20	1130	1047	0	0
T21	2411	2189	0	0
T22	2141	2113	0	0
T23	1703	1629	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146591435	112360	0	0
DstReqKnown_A	215490114	213342118	0	0
SrcAckBusyChk_A	146591435	21732	0	0
SrcBusyKnown_A	146591435	144130708	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	112360	0	0
T1	111257	359	0	0
T2	0	1918	0	0
T3	0	115	0	0
T4	0	65	0	0
T5	195822	266	0	0
T6	12425	22	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	1256	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	21	0	0
T26	0	85	0	0
T29	0	123	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215490114	213342118	0	0
T1	513885	513249	0	0
T5	85356	85075	0	0
T6	12691	12589	0	0
T7	1842	1761	0	0
T8	1057	949	0	0
T19	2472	2411	0	0
T20	1106	1026	0	0
T21	1180	1072	0	0
T22	4111	4058	0	0
T23	2820	2698	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	21732	0	0
T1	111257	138	0	0
T2	0	770	0	0
T3	0	32	0	0
T4	0	7	0	0
T5	195822	32	0	0
T6	12425	4	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	158	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	6	0	0
T26	0	19	0	0
T29	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	144130708	0	0
T1	111257	111128	0	0
T5	195822	195239	0	0
T6	12425	12326	0	0
T7	920	880	0	0
T8	2138	1918	0	0
T19	926	904	0	0
T20	1130	1047	0	0
T21	2411	2189	0	0
T22	2141	2113	0	0
T23	1703	1629	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T2,T4,T26
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146591435	102484	0	0
DstReqKnown_A	421156755	416910288	0	0
SrcAckBusyChk_A	146591435	28133	0	0
SrcBusyKnown_A	146591435	144130708	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	102484	0	0
T1	111257	360	0	0
T2	0	1938	0	0
T3	0	85	0	0
T4	0	135	0	0
T5	195822	168	0	0
T6	12425	15	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	985	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	15	0	0
T26	0	190	0	0
T29	0	89	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421156755	416910288	0	0
T1	929807	928534	0	0
T5	164947	164387	0	0
T6	25380	25177	0	0
T7	3685	3523	0	0
T8	2115	1898	0	0
T19	4943	4822	0	0
T20	2213	2051	0	0
T21	2361	2144	0	0
T22	8223	8116	0	0
T23	5640	5395	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	28133	0	0
T1	111257	138	0	0
T2	0	780	0	0
T3	0	32	0	0
T4	0	28	0	0
T5	195822	32	0	0
T6	12425	4	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	165	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	6	0	0
T26	0	76	0	0
T29	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	144130708	0	0
T1	111257	111128	0	0
T5	195822	195239	0	0
T6	12425	12326	0	0
T7	920	880	0	0
T8	2138	1918	0	0
T19	926	904	0	0
T20	1130	1047	0	0
T21	2411	2189	0	0
T22	2141	2113	0	0
T23	1703	1629	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T2,T4,T26
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146591435	147219	0	0
DstReqKnown_A	209762806	208680602	0	0
SrcAckBusyChk_A	146591435	28010	0	0
SrcBusyKnown_A	146591435	144130708	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	147219	0	0
T1	111257	360	0	0
T2	0	1938	0	0
T3	0	117	0	0
T4	0	218	0	0
T5	195822	271	0	0
T6	12425	22	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	1392	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	21	0	0
T26	0	228	0	0
T29	0	123	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209762806	208680602	0	0
T1	466402	466058	0	0
T5	82351	82193	0	0
T6	12657	12588	0	0
T7	1875	1861	0	0
T8	1071	1016	0	0
T19	2485	2437	0	0
T20	1070	1042	0	0
T21	1249	1187	0	0
T22	4577	4556	0	0
T23	3127	3065	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	28010	0	0
T1	111257	138	0	0
T2	0	780	0	0
T3	0	32	0	0
T4	0	28	0	0
T5	195822	32	0	0
T6	12425	4	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	165	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	6	0	0
T26	0	76	0	0
T29	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	144130708	0	0
T1	111257	111128	0	0
T5	195822	195239	0	0
T6	12425	12326	0	0
T7	920	880	0	0
T8	2138	1918	0	0
T19	926	904	0	0
T20	1130	1047	0	0
T21	2411	2189	0	0
T22	2141	2113	0	0
T23	1703	1629	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T2,T4,T26
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146591435	237328	0	0
DstReqKnown_A	104880891	104339908	0	0
SrcAckBusyChk_A	146591435	28014	0	0
SrcBusyKnown_A	146591435	144130708	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	237328	0	0
T1	111257	481	0	0
T2	0	2316	0	0
T3	0	170	0	0
T4	0	367	0	0
T5	195822	472	0	0
T6	12425	34	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	2424	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	30	0	0
T26	0	304	0	0
T29	0	178	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104880891	104339908	0	0
T1	233200	233029	0	0
T5	41176	41097	0	0
T6	6329	6295	0	0
T7	938	931	0	0
T8	534	506	0	0
T19	1242	1218	0	0
T20	535	521	0	0
T21	625	594	0	0
T22	2286	2276	0	0
T23	1562	1531	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	28014	0	0
T1	111257	138	0	0
T2	0	780	0	0
T3	0	32	0	0
T4	0	28	0	0
T5	195822	32	0	0
T6	12425	4	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	165	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	6	0	0
T26	0	76	0	0
T29	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	144130708	0	0
T1	111257	111128	0	0
T5	195822	195239	0	0
T6	12425	12326	0	0
T7	920	880	0	0
T8	2138	1918	0	0
T19	926	904	0	0
T20	1130	1047	0	0
T21	2411	2189	0	0
T22	2141	2113	0	0
T23	1703	1629	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T2,T4,T26
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146591435	101306	0	0
DstReqKnown_A	448407550	443971145	0	0
SrcAckBusyChk_A	146591435	28148	0	0
SrcBusyKnown_A	146591435	144130708	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	101306	0	0
T1	111257	360	0	0
T2	0	1938	0	0
T3	0	81	0	0
T4	0	132	0	0
T5	195822	196	0	0
T6	12425	15	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	799	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	15	0	0
T26	0	190	0	0
T29	0	89	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448407550	443971145	0	0
T1	107657	107525	0	0
T5	153822	153239	0	0
T6	20438	20226	0	0
T7	3838	3669	0	0
T8	2203	1977	0	0
T19	5149	5023	0	0
T20	2305	2136	0	0
T21	2459	2233	0	0
T22	8566	8454	0	0
T23	5875	5620	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	28148	0	0
T1	111257	138	0	0
T2	0	780	0	0
T3	0	32	0	0
T4	0	28	0	0
T5	195822	32	0	0
T6	12425	4	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	165	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	6	0	0
T26	0	76	0	0
T29	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	144130708	0	0
T1	111257	111128	0	0
T5	195822	195239	0	0
T6	12425	12326	0	0
T7	920	880	0	0
T8	2138	1918	0	0
T19	926	904	0	0
T20	1130	1047	0	0
T21	2411	2189	0	0
T22	2141	2113	0	0
T23	1703	1629	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T2,T4,T26
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T7,T8
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146591435	147441	0	0
DstReqKnown_A	215490114	213342118	0	0
SrcAckBusyChk_A	146591435	27770	0	0
SrcBusyKnown_A	146591435	144130708	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	147441	0	0
T1	111257	360	0	0
T2	0	1938	0	0
T3	0	113	0	0
T4	0	213	0	0
T5	195822	266	0	0
T6	12425	22	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	1317	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	21	0	0
T26	0	228	0	0
T29	0	123	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215490114	213342118	0	0
T1	513885	513249	0	0
T5	85356	85075	0	0
T6	12691	12589	0	0
T7	1842	1761	0	0
T8	1057	949	0	0
T19	2472	2411	0	0
T20	1106	1026	0	0
T21	1180	1072	0	0
T22	4111	4058	0	0
T23	2820	2698	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	27770	0	0
T1	111257	138	0	0
T2	0	780	0	0
T3	0	32	0	0
T4	0	24	0	0
T5	195822	32	0	0
T6	12425	4	0	0
T7	920	0	0	0
T8	2138	0	0	0
T12	0	165	0	0
T19	926	0	0	0
T20	1130	0	0	0
T21	2411	0	0	0
T22	2141	0	0	0
T23	1703	0	0	0
T24	0	6	0	0
T26	0	75	0	0
T29	0	34	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146591435	144130708	0	0
T1	111257	111128	0	0
T5	195822	195239	0	0
T6	12425	12326	0	0
T7	920	880	0	0
T8	2138	1918	0	0
T19	926	904	0	0
T20	1130	1047	0	0
T21	2411	2189	0	0
T22	2141	2113	0	0
T23	1703	1629	0	0