Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T7,T8
1	1	Covered	T5,T7,T8

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	45611	0	0
CgEnOn_A	2147483647	36853	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45611	0	0
T1	1737066	116	0	0
T2	493126	113	0	0
T5	288474	45	0	0
T6	64804	3	0	0
T7	6498	3	0	0
T8	3720	3	0	0
T9	81456	0	0	0
T12	1365250	24	0	0
T13	2381470	0	0	0
T14	1800708	0	0	0
T19	13819	3	0	0
T20	6123	3	0	0
T21	6694	3	0	0
T22	23652	3	0	0
T23	16204	3	0	0
T32	3437	0	0	0
T37	2680	18	0	0
T38	0	15	0	0
T39	0	15	0	0
T62	0	5	0	0
T63	0	5	0	0
T72	159282	0	0	0
T98	165193	0	0	0
T106	11575	0	0	0
T111	12695	0	0	0
T141	0	5	0	0
T142	0	10	0	0
T143	0	15	0	0
T144	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36853	0	0
T1	1737066	92	0	0
T2	493126	603	0	0
T5	288474	36	0	0
T6	64804	0	0	0
T7	6498	0	0	0
T8	3720	0	0	0
T9	81456	0	0	0
T12	1365250	314	0	0
T13	2381470	131	0	0
T14	1800708	154	0	0
T15	0	282	0	0
T17	0	79	0	0
T19	13819	0	0	0
T20	6123	0	0	0
T21	6694	0	0	0
T22	23652	0	0	0
T23	16204	0	0	0
T25	0	44	0	0
T32	3437	0	0	0
T37	2680	27	0	0
T38	0	15	0	0
T39	0	15	0	0
T62	0	4	0	0
T63	0	4	0	0
T68	0	10	0	0
T72	159282	0	0	0
T98	165193	0	0	0
T106	11575	0	0	0
T111	12695	0	0	0
T141	0	5	0	0
T142	0	10	0	0
T143	0	15	0	0
T144	0	10	0	0
T145	0	3	0	0
T146	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	208649248	154	0	0
CgEnOn_A	208649248	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208649248	154	0	0
T9	12654	0	0	0
T12	505531	1	0	0
T13	881574	0	0	0
T14	100039	0	0	0
T32	746	0	0	0
T37	590	3	0	0
T38	0	3	0	0
T39	0	3	0	0
T62	0	1	0	0
T63	0	1	0	0
T72	25994	0	0	0
T98	29538	0	0	0
T106	2555	0	0	0
T111	2922	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208649248	154	0	0
T9	12654	0	0	0
T12	505531	1	0	0
T13	881574	0	0	0
T14	100039	0	0	0
T32	746	0	0	0
T37	590	3	0	0
T38	0	3	0	0
T39	0	3	0	0
T62	0	1	0	0
T63	0	1	0	0
T72	25994	0	0	0
T98	29538	0	0	0
T106	2555	0	0	0
T111	2922	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104324119	154	0	0
CgEnOn_A	104324119	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104324119	154	0	0
T9	6327	0	0	0
T12	252759	1	0	0
T13	440783	0	0	0
T14	500195	0	0	0
T32	373	0	0	0
T37	295	3	0	0
T38	0	3	0	0
T39	0	3	0	0
T62	0	1	0	0
T63	0	1	0	0
T72	12997	0	0	0
T98	14769	0	0	0
T106	1277	0	0	0
T111	1460	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104324119	154	0	0
T9	6327	0	0	0
T12	252759	1	0	0
T13	440783	0	0	0
T14	500195	0	0	0
T32	373	0	0	0
T37	295	3	0	0
T38	0	3	0	0
T39	0	3	0	0
T62	0	1	0	0
T63	0	1	0	0
T72	12997	0	0	0
T98	14769	0	0	0
T106	1277	0	0	0
T111	1460	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	418836349	154	0	0
CgEnOn_A	418836349	148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418836349	154	0	0
T9	49821	0	0	0
T12	101442	1	0	0
T13	177547	0	0	0
T14	200084	0	0	0
T32	1572	0	0	0
T37	1205	3	0	0
T38	0	3	0	0
T39	0	3	0	0
T62	0	1	0	0
T63	0	1	0	0
T72	94297	0	0	0
T98	91348	0	0	0
T106	5189	0	0	0
T111	5393	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418836349	148	0	0
T9	49821	0	0	0
T12	101442	1	0	0
T13	177547	0	0	0
T14	200084	0	0	0
T32	1572	0	0	0
T37	1205	3	0	0
T38	0	3	0	0
T39	0	3	0	0
T72	94297	0	0	0
T98	91348	0	0	0
T106	5189	0	0	0
T111	5393	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	3	0	0
T146	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	445990359	153	0	0
CgEnOn_A	445990359	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990359	153	0	0
T9	51898	0	0	0
T12	112773	0	0	0
T13	192337	1	0	0
T14	210604	0	0	0
T32	1637	0	0	0
T37	1239	3	0	0
T38	0	2	0	0
T39	0	4	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T72	98228	0	0	0
T98	95158	0	0	0
T106	5405	0	0	0
T111	5618	0	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990359	147	0	0
T9	51898	0	0	0
T12	112773	0	0	0
T13	192337	0	0	0
T14	210604	0	0	0
T32	1637	0	0	0
T37	1239	3	0	0
T38	0	2	0	0
T39	0	4	0	0
T72	98228	0	0	0
T98	95158	0	0	0
T106	5405	0	0	0
T111	5618	0	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	4	0	0
T146	0	1	0	0
T147	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104324119	154	0	0
CgEnOn_A	104324119	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104324119	154	0	0
T9	6327	0	0	0
T12	252759	1	0	0
T13	440783	0	0	0
T14	500195	0	0	0
T32	373	0	0	0
T37	295	3	0	0
T38	0	3	0	0
T39	0	3	0	0
T62	0	1	0	0
T63	0	1	0	0
T72	12997	0	0	0
T98	14769	0	0	0
T106	1277	0	0	0
T111	1460	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104324119	154	0	0
T9	6327	0	0	0
T12	252759	1	0	0
T13	440783	0	0	0
T14	500195	0	0	0
T32	373	0	0	0
T37	295	3	0	0
T38	0	3	0	0
T39	0	3	0	0
T62	0	1	0	0
T63	0	1	0	0
T72	12997	0	0	0
T98	14769	0	0	0
T106	1277	0	0	0
T111	1460	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	445990359	153	0	0
CgEnOn_A	445990359	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990359	153	0	0
T9	51898	0	0	0
T12	112773	0	0	0
T13	192337	1	0	0
T14	210604	0	0	0
T32	1637	0	0	0
T37	1239	3	0	0
T38	0	2	0	0
T39	0	4	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T72	98228	0	0	0
T98	95158	0	0	0
T106	5405	0	0	0
T111	5618	0	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990359	147	0	0
T9	51898	0	0	0
T12	112773	0	0	0
T13	192337	0	0	0
T14	210604	0	0	0
T32	1637	0	0	0
T37	1239	3	0	0
T38	0	2	0	0
T39	0	4	0	0
T72	98228	0	0	0
T98	95158	0	0	0
T106	5405	0	0	0
T111	5618	0	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	4	0	0
T146	0	1	0	0
T147	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104324119	154	0	0
CgEnOn_A	104324119	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104324119	154	0	0
T9	6327	0	0	0
T12	252759	1	0	0
T13	440783	0	0	0
T14	500195	0	0	0
T32	373	0	0	0
T37	295	3	0	0
T38	0	3	0	0
T39	0	3	0	0
T62	0	1	0	0
T63	0	1	0	0
T72	12997	0	0	0
T98	14769	0	0	0
T106	1277	0	0	0
T111	1460	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104324119	154	0	0
T9	6327	0	0	0
T12	252759	1	0	0
T13	440783	0	0	0
T14	500195	0	0	0
T32	373	0	0	0
T37	295	3	0	0
T38	0	3	0	0
T39	0	3	0	0
T62	0	1	0	0
T63	0	1	0	0
T72	12997	0	0	0
T98	14769	0	0	0
T106	1277	0	0	0
T111	1460	0	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	0	3	0	0
T144	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T5,T7,T8
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	208649248	7308	0	0
CgEnOn_A	208649248	5132	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208649248	7308	0	0
T1	466402	33	0	0
T5	82351	14	0	0
T6	12657	1	0	0
T7	1875	1	0	0
T8	1071	1	0	0
T19	2485	1	0	0
T20	1070	1	0	0
T21	1249	1	0	0
T22	4577	1	0	0
T23	3127	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208649248	5132	0	0
T1	466402	25	0	0
T2	0	166	0	0
T5	82351	11	0	0
T6	12657	0	0	0
T7	1875	0	0	0
T8	1071	0	0	0
T12	0	95	0	0
T13	0	39	0	0
T14	0	51	0	0
T15	0	93	0	0
T17	0	25	0	0
T19	2485	0	0	0
T20	1070	0	0	0
T21	1249	0	0	0
T22	4577	0	0	0
T23	3127	0	0	0
T25	0	15	0	0
T37	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T5,T7,T8
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104324119	7234	0	0
CgEnOn_A	104324119	5058	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104324119	7234	0	0
T1	233200	31	0	0
T5	41176	15	0	0
T6	6329	1	0	0
T7	938	1	0	0
T8	534	1	0	0
T19	1242	1	0	0
T20	535	1	0	0
T21	625	1	0	0
T22	2286	1	0	0
T23	1562	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104324119	5058	0	0
T1	233200	23	0	0
T2	0	166	0	0
T5	41176	12	0	0
T6	6329	0	0	0
T7	938	0	0	0
T8	534	0	0	0
T12	0	98	0	0
T13	0	37	0	0
T14	0	52	0	0
T15	0	94	0	0
T17	0	27	0	0
T19	1242	0	0	0
T20	535	0	0	0
T21	625	0	0	0
T22	2286	0	0	0
T23	1562	0	0	0
T25	0	13	0	0
T37	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T5,T7,T8
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	418836349	7319	0	0
CgEnOn_A	418836349	5137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418836349	7319	0	0
T1	929807	32	0	0
T5	164947	16	0	0
T6	25380	1	0	0
T7	3685	1	0	0
T8	2115	1	0	0
T19	4943	1	0	0
T20	2213	1	0	0
T21	2361	1	0	0
T22	8223	1	0	0
T23	5640	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418836349	5137	0	0
T1	929807	24	0	0
T2	0	158	0	0
T5	164947	13	0	0
T6	25380	0	0	0
T7	3685	0	0	0
T8	2115	0	0	0
T12	0	97	0	0
T13	0	35	0	0
T14	0	51	0	0
T15	0	95	0	0
T17	0	27	0	0
T19	4943	0	0	0
T20	2213	0	0	0
T21	2361	0	0	0
T22	8223	0	0	0
T23	5640	0	0	0
T25	0	15	0	0
T37	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T5,T7,T8
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	214329890	7283	0	0
CgEnOn_A	214329890	5101	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214329890	7283	0	0
T1	513885	35	0	0
T5	85356	14	0	0
T6	12691	1	0	0
T7	1842	1	0	0
T8	1057	1	0	0
T19	2472	1	0	0
T20	1106	1	0	0
T21	1180	1	0	0
T22	4111	1	0	0
T23	2820	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214329890	5101	0	0
T1	513885	27	0	0
T2	0	160	0	0
T5	85356	11	0	0
T6	12691	0	0	0
T7	1842	0	0	0
T8	1057	0	0	0
T12	0	98	0	0
T13	0	37	0	0
T14	0	52	0	0
T15	0	91	0	0
T17	0	26	0	0
T19	2472	0	0	0
T20	1106	0	0	0
T21	1180	0	0	0
T22	4111	0	0	0
T23	2820	0	0	0
T25	0	14	0	0
T37	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T2,T25
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	445990359	3870	0	0
CgEnOn_A	445990359	3864	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990359	3870	0	0
T1	107657	20	0	0
T2	493126	113	0	0
T6	20438	0	0	0
T12	0	19	0	0
T13	0	21	0	0
T19	5149	0	0	0
T20	2305	0	0	0
T21	2459	0	0	0
T22	8566	0	0	0
T23	5875	0	0	0
T24	34145	0	0	0
T25	6794	1	0	0
T37	0	3	0	0
T68	0	10	0	0
T70	0	2	0	0
T71	0	7	0	0
T106	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990359	3864	0	0
T1	107657	20	0	0
T2	493126	113	0	0
T6	20438	0	0	0
T12	0	19	0	0
T13	0	20	0	0
T19	5149	0	0	0
T20	2305	0	0	0
T21	2459	0	0	0
T22	8566	0	0	0
T23	5875	0	0	0
T24	34145	0	0	0
T25	6794	1	0	0
T37	0	3	0	0
T68	0	10	0	0
T70	0	2	0	0
T71	0	7	0	0
T106	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T2,T25
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	445990359	3905	0	0
CgEnOn_A	445990359	3899	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990359	3905	0	0
T1	107657	22	0	0
T2	493126	122	0	0
T6	20438	0	0	0
T12	0	17	0	0
T13	0	20	0	0
T19	5149	0	0	0
T20	2305	0	0	0
T21	2459	0	0	0
T22	8566	0	0	0
T23	5875	0	0	0
T24	34145	0	0	0
T25	6794	1	0	0
T37	0	3	0	0
T68	0	9	0	0
T70	0	4	0	0
T71	0	5	0	0
T106	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990359	3899	0	0
T1	107657	22	0	0
T2	493126	122	0	0
T6	20438	0	0	0
T12	0	17	0	0
T13	0	19	0	0
T19	5149	0	0	0
T20	2305	0	0	0
T21	2459	0	0	0
T22	8566	0	0	0
T23	5875	0	0	0
T24	34145	0	0	0
T25	6794	1	0	0
T37	0	3	0	0
T68	0	9	0	0
T70	0	4	0	0
T71	0	5	0	0
T106	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T2,T25
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	445990359	3819	0	0
CgEnOn_A	445990359	3813	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990359	3819	0	0
T1	107657	21	0	0
T2	493126	102	0	0
T6	20438	0	0	0
T12	0	19	0	0
T13	0	23	0	0
T14	0	87	0	0
T19	5149	0	0	0
T20	2305	0	0	0
T21	2459	0	0	0
T22	8566	0	0	0
T23	5875	0	0	0
T24	34145	0	0	0
T25	6794	1	0	0
T37	0	3	0	0
T68	0	5	0	0
T70	0	1	0	0
T71	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990359	3813	0	0
T1	107657	21	0	0
T2	493126	102	0	0
T6	20438	0	0	0
T12	0	19	0	0
T13	0	22	0	0
T14	0	87	0	0
T19	5149	0	0	0
T20	2305	0	0	0
T21	2459	0	0	0
T22	8566	0	0	0
T23	5875	0	0	0
T24	34145	0	0	0
T25	6794	1	0	0
T37	0	3	0	0
T68	0	5	0	0
T70	0	1	0	0
T71	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T1,T2,T25
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	445990359	3797	0	0
CgEnOn_A	445990359	3791	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990359	3797	0	0
T1	107657	22	0	0
T2	493126	114	0	0
T6	20438	0	0	0
T12	0	18	0	0
T13	0	22	0	0
T19	5149	0	0	0
T20	2305	0	0	0
T21	2459	0	0	0
T22	8566	0	0	0
T23	5875	0	0	0
T24	34145	0	0	0
T25	6794	1	0	0
T37	0	3	0	0
T68	0	7	0	0
T70	0	3	0	0
T71	0	7	0	0
T106	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990359	3791	0	0
T1	107657	22	0	0
T2	493126	114	0	0
T6	20438	0	0	0
T12	0	18	0	0
T13	0	21	0	0
T19	5149	0	0	0
T20	2305	0	0	0
T21	2459	0	0	0
T22	8566	0	0	0
T23	5875	0	0	0
T24	34145	0	0	0
T25	6794	1	0	0
T37	0	3	0	0
T68	0	7	0	0
T70	0	3	0	0
T71	0	7	0	0
T106	0	1	0	0