Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	583701	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3294894

1

T6

29

T5

27

T1

89

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	952687	1			T6	40		T5	3		T1	20
values[0x0]	1344165	1			T6	19		T5	22		T1	92
values[0x1]	1581743	1			T6	11		T5	42		T1	78

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	323886	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3554709

1

T6

40

T5

37

T1

119

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14539	1			T2	517		T4	1		T33	1
valid_sources[0x01]	15116	1			T2	10		T4	2		T26	1
valid_sources[0x02]	14876	1			T6	70		T2	180		T4	1
valid_sources[0x03]	14530	1			T16	2		T2	363		T4	5
valid_sources[0x04]	15358	1			T2	259		T4	11		T33	2
valid_sources[0x05]	14335	1			T2	75		T4	3		T31	1
valid_sources[0x06]	16647	1			T20	1		T22	1		T2	3
valid_sources[0x07]	15770	1			T23	1		T2	708		T4	8
valid_sources[0x08]	13899	1			T16	2		T2	162		T33	2
valid_sources[0x09]	14260	1			T22	3		T2	119		T4	4
valid_sources[0x0a]	17437	1			T2	331		T4	5		T31	1
valid_sources[0x0b]	15237	1			T22	1		T2	228		T30	1
valid_sources[0x0c]	14451	1			T2	384		T4	4		T27	1
valid_sources[0x0d]	14682	1			T22	2		T2	437		T9	381
valid_sources[0x0e]	15564	1			T2	69		T4	2		T34	2
valid_sources[0x0f]	14530	1			T16	1		T2	204		T4	4
valid_sources[0x10]	15771	1			T2	693		T4	2		T28	2
valid_sources[0x11]	14885	1			T16	1		T23	1		T2	402
valid_sources[0x12]	14162	1			T2	152		T4	2		T27	1
valid_sources[0x13]	14768	1			T20	1		T22	1		T2	244
valid_sources[0x14]	14909	1			T16	1		T2	297		T4	4
valid_sources[0x15]	16356	1			T2	1084		T4	2		T27	1
valid_sources[0x16]	15928	1			T2	119		T4	6		T34	2
valid_sources[0x17]	16468	1			T2	417		T4	3		T33	3
valid_sources[0x18]	14038	1			T2	12		T4	5		T33	2
valid_sources[0x19]	14177	1			T4	3		T33	1		T9	411
valid_sources[0x1a]	18133	1			T16	2		T23	1		T2	587
valid_sources[0x1b]	16091	1			T2	296		T4	2		T30	1
valid_sources[0x1c]	15552	1			T22	1		T2	199		T4	3
valid_sources[0x1d]	15232	1			T2	443		T4	1		T7	1
valid_sources[0x1e]	16280	1			T2	136		T4	3		T7	1
valid_sources[0x1f]	14517	1			T2	153		T4	6		T28	1
valid_sources[0x20]	14745	1			T2	158		T4	2		T34	7
valid_sources[0x21]	14963	1			T2	165		T30	3		T31	1
valid_sources[0x22]	14883	1			T22	1		T2	203		T4	3
valid_sources[0x23]	16688	1			T22	1		T2	547		T4	2
valid_sources[0x24]	14727	1			T2	137		T4	2		T26	2
valid_sources[0x25]	15611	1			T20	1		T22	1		T2	289
valid_sources[0x26]	14753	1			T4	2		T34	2		T9	390
valid_sources[0x27]	16326	1			T22	1		T2	335		T4	1
valid_sources[0x28]	14844	1			T16	1		T22	1		T23	1
valid_sources[0x29]	16078	1			T2	260		T4	4		T30	1
valid_sources[0x2a]	14405	1			T22	1		T2	181		T4	1
valid_sources[0x2b]	14596	1			T22	1		T2	211		T4	2
valid_sources[0x2c]	15835	1			T2	317		T4	7		T99	4
valid_sources[0x2d]	16220	1			T23	1		T2	493		T4	3
valid_sources[0x2e]	15576	1			T22	1		T2	826		T4	1
valid_sources[0x2f]	14058	1			T2	174		T4	3		T27	1
valid_sources[0x30]	14233	1			T16	1		T22	2		T4	5
valid_sources[0x31]	20414	1			T2	219		T7	1		T30	4
valid_sources[0x32]	15729	1			T2	272		T4	1		T28	6
valid_sources[0x33]	15268	1			T2	63		T4	2		T28	2
valid_sources[0x34]	14127	1			T2	22		T4	5		T34	1
valid_sources[0x35]	13843	1			T23	1		T2	334		T4	4
valid_sources[0x36]	14911	1			T23	1		T2	27		T4	3
valid_sources[0x37]	15713	1			T22	1		T23	1		T2	159
valid_sources[0x38]	15877	1			T16	1		T2	37		T4	3
valid_sources[0x39]	14665	1			T22	1		T2	23		T4	3
valid_sources[0x3a]	16475	1			T2	31		T4	7		T27	1
valid_sources[0x3b]	15128	1			T2	107		T37	1		T9	411
valid_sources[0x3c]	17072	1			T2	909		T4	3		T7	1
valid_sources[0x3d]	15052	1			T5	21		T2	96		T4	3
valid_sources[0x3e]	14905	1			T22	1		T23	1		T2	84
valid_sources[0x3f]	15675	1			T23	2		T2	178		T4	3
valid_sources[0x40]	13790	1			T2	102		T4	3		T33	3
valid_sources[0x41]	16178	1			T22	1		T2	306		T4	3
valid_sources[0x42]	14787	1			T2	247		T4	3		T31	1
valid_sources[0x43]	15830	1			T5	1		T2	333		T4	1
valid_sources[0x44]	14657	1			T2	91		T7	1		T33	3
valid_sources[0x45]	15116	1			T2	309		T4	5		T99	9
valid_sources[0x46]	14528	1			T2	26		T4	1		T28	6
valid_sources[0x47]	13796	1			T2	183		T4	3		T31	1
valid_sources[0x48]	14096	1			T2	188		T4	1		T34	4
valid_sources[0x49]	14873	1			T16	1		T22	2		T23	2
valid_sources[0x4a]	15079	1			T2	809		T4	5		T30	1
valid_sources[0x4b]	15181	1			T2	141		T4	6		T27	1
valid_sources[0x4c]	14793	1			T5	1		T4	4		T27	1
valid_sources[0x4d]	15914	1			T22	1		T23	1		T2	452
valid_sources[0x4e]	14034	1			T1	190		T2	16		T4	3
valid_sources[0x4f]	14260	1			T22	1		T2	129		T4	2
valid_sources[0x50]	14048	1			T2	13		T4	3		T27	1
valid_sources[0x51]	14870	1			T22	1		T4	1		T26	1
valid_sources[0x52]	15373	1			T2	631		T4	2		T30	3
valid_sources[0x53]	15009	1			T5	2		T2	118		T4	3
valid_sources[0x54]	14737	1			T23	1		T2	356		T4	1
valid_sources[0x55]	14792	1			T2	65		T4	2		T31	1
valid_sources[0x56]	13485	1			T22	1		T2	301		T33	1
valid_sources[0x57]	15190	1			T2	669		T26	7		T27	1
valid_sources[0x58]	14703	1			T22	2		T23	2		T2	160
valid_sources[0x59]	15075	1			T16	3		T20	9		T2	243
valid_sources[0x5a]	13701	1			T22	1		T2	51		T4	3
valid_sources[0x5b]	14988	1			T20	11		T2	287		T4	4
valid_sources[0x5c]	15890	1			T22	2		T2	1		T4	4
valid_sources[0x5d]	14410	1			T4	6		T100	1		T34	1
valid_sources[0x5e]	15658	1			T16	2		T2	227		T4	4
valid_sources[0x5f]	15165	1			T16	1		T2	649		T4	4
valid_sources[0x60]	14470	1			T23	2		T2	151		T4	3
valid_sources[0x61]	14638	1			T22	1		T2	272		T4	4
valid_sources[0x62]	15866	1			T22	1		T2	18		T4	3
valid_sources[0x63]	14960	1			T19	24		T2	232		T28	9
valid_sources[0x64]	14699	1			T22	1		T2	531		T4	2
valid_sources[0x65]	14485	1			T2	318		T4	6		T30	1
valid_sources[0x66]	13538	1			T2	120		T4	2		T7	2
valid_sources[0x67]	13847	1			T4	1		T28	1		T34	1
valid_sources[0x68]	14786	1			T23	1		T4	1		T99	2
valid_sources[0x69]	13390	1			T2	149		T4	7		T28	5
valid_sources[0x6a]	14139	1			T2	280		T4	2		T26	11
valid_sources[0x6b]	15136	1			T4	3		T28	3		T34	4
valid_sources[0x6c]	16274	1			T23	1		T2	419		T4	3
valid_sources[0x6d]	15596	1			T22	1		T2	1		T4	5
valid_sources[0x6e]	14307	1			T2	255		T4	4		T33	1
valid_sources[0x6f]	15481	1			T22	2		T23	1		T2	961
valid_sources[0x70]	15668	1			T16	1		T2	36		T4	5
valid_sources[0x71]	14580	1			T5	3		T2	128		T4	3
valid_sources[0x72]	14331	1			T2	24		T4	5		T7	1
valid_sources[0x73]	15510	1			T2	106		T4	2		T7	1
valid_sources[0x74]	14705	1			T2	5		T4	6		T27	1
valid_sources[0x75]	14535	1			T2	255		T4	4		T33	3
valid_sources[0x76]	14735	1			T22	2		T4	4		T33	2
valid_sources[0x77]	14656	1			T2	192		T34	2		T9	420
valid_sources[0x78]	15462	1			T2	411		T4	3		T27	1
valid_sources[0x79]	15521	1			T22	1		T2	282		T4	4
valid_sources[0x7a]	16221	1			T23	1		T2	123		T30	1
valid_sources[0x7b]	13870	1			T4	2		T34	1		T9	409
valid_sources[0x7c]	15317	1			T22	2		T2	459		T4	2
valid_sources[0x7d]	14794	1			T2	76		T4	1		T30	1
valid_sources[0x7e]	15369	1			T4	5		T7	1		T33	2
valid_sources[0x7f]	15263	1			T2	217		T4	5		T100	1
valid_sources[0x80]	14341	1			T2	316		T4	10		T27	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

830355

1

T6

22

T5

2

T1

9

values[0x0]

all_enables

biggest_size

1254166

1

T6

6

T5

11

T1

53

values[0x1]

all_enables

biggest_size

1210373

1

T6

1

T5

14

T1

27