SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[clkmgr_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 10608191 | 0 | T6 | 70 | T5 | 67 | T1 | 190 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 10608013 | 1 | T6 | 70 | T5 | 67 | T1 | 190 | ||||
values[1] | 16 | 1 | T93 | 3 | T89 | 1 | T82 | 1 | ||||
values[2] | 4 | 1 | T79 | 2 | T163 | 1 | T164 | 1 | ||||
values[3] | 84 | 1 | T79 | 3 | T80 | 6 | T81 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 10607953 | 1 | T6 | 70 | T5 | 67 | T1 | 190 | ||||
values[1] | 27 | 1 | T79 | 1 | T80 | 3 | T93 | 1 | ||||
values[2] | 8 | 1 | T79 | 1 | T92 | 1 | T165 | 1 | ||||
values[3] | 113 | 1 | T79 | 2 | T80 | 5 | T81 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 10607881 | 1 | T6 | 70 | T5 | 67 | T1 | 190 | ||||
auto[TlIntgErrCmd] | 72 | 1 | T79 | 3 | T80 | 6 | T81 | 4 | ||||
auto[TlIntgErrData] | 132 | 1 | T79 | 2 | T80 | 8 | T81 | 3 | ||||
auto[TlIntgErrBoth] | 106 | 1 | T79 | 5 | T80 | 6 | T81 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |