Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T21
0	1	Covered	T2,T3,T9
1	0	Covered	T6,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T22,T2
1	0	Covered	T17,T21,T40
1	1	Covered	T6,T5,T1

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1010394232	13097	0	0
GateOpen_A	1010394232	19432	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010394232	13097	0	0
T2	1044782	114	0	0
T3	0	36	0	0
T4	190166	0	0	0
T7	1842	0	0	0
T9	0	224	0	0
T10	0	55	0	0
T17	6139	3	0	0
T18	2599	0	0	0
T19	3836	0	0	0
T20	4158	0	0	0
T21	2395	1	0	0
T22	10425	4	0	0
T23	4553	0	0	0
T26	50644	0	0	0
T27	1565	0	0	0
T28	1813	0	0	0
T29	991	0	0	0
T40	0	17	0	0
T41	0	16	0	0
T59	0	45	0	0
T162	0	39	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010394232	19432	0	0
T1	198771	4	0	0
T2	0	126	0	0
T4	0	64	0	0
T5	51899	4	0	0
T16	32207	200	0	0
T17	7927	7	0	0
T18	3362	0	0	0
T19	4954	0	0	0
T20	5324	4	0	0
T21	2395	5	0	0
T22	10425	4	0	0
T23	4553	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T22
0	1	Covered	T2,T3,T9
1	0	Covered	T6,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T22,T2
1	0	Covered	T17,T40,T41
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	111443140	3123	0	0
GateOpen_A	111443140	4705	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111443140	3123	0	0
T2	577261	30	0	0
T3	0	9	0	0
T4	12567	0	0	0
T9	0	53	0	0
T10	0	13	0	0
T17	872	1	0	0
T18	358	0	0	0
T19	533	0	0	0
T20	608	0	0	0
T21	263	0	0	0
T22	1152	1	0	0
T23	542	0	0	0
T26	5623	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T59	0	11	0	0
T162	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111443140	4705	0	0
T1	22075	1	0	0
T2	0	33	0	0
T4	0	16	0	0
T5	4794	1	0	0
T16	2757	50	0	0
T17	872	2	0	0
T18	358	0	0	0
T19	533	0	0	0
T20	608	1	0	0
T21	263	1	0	0
T22	1152	1	0	0
T23	542	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T22
0	1	Covered	T2,T3,T9
1	0	Covered	T6,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T22,T2
1	0	Covered	T17,T40,T41
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	222887096	3300	0	0
GateOpen_A	222887096	4882	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222887096	3300	0	0
T2	115452	26	0	0
T3	0	10	0	0
T4	25133	0	0	0
T9	0	57	0	0
T10	0	12	0	0
T17	1743	1	0	0
T18	716	0	0	0
T19	1065	0	0	0
T20	1219	0	0	0
T21	525	0	0	0
T22	2304	1	0	0
T23	1086	0	0	0
T26	11246	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T59	0	13	0	0
T162	0	11	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222887096	4882	0	0
T1	44149	1	0	0
T2	0	29	0	0
T4	0	16	0	0
T5	9587	1	0	0
T16	5509	50	0	0
T17	1743	2	0	0
T18	716	0	0	0
T19	1065	0	0	0
T20	1219	1	0	0
T21	525	1	0	0
T22	2304	1	0	0
T23	1086	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T22
0	1	Covered	T2,T3,T9
1	0	Covered	T6,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T22,T2
1	0	Covered	T17,T40,T41
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	447206562	3339	0	0
GateOpen_A	447206562	4924	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447206562	3339	0	0
T2	231811	27	0	0
T3	0	9	0	0
T4	101642	0	0	0
T9	0	59	0	0
T10	0	16	0	0
T17	3524	1	0	0
T18	1525	0	0	0
T19	2238	0	0	0
T20	2331	0	0	0
T21	1075	0	0	0
T22	4646	1	0	0
T23	1950	0	0	0
T26	22516	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T59	0	10	0	0
T162	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447206562	4924	0	0
T1	88363	1	0	0
T2	0	30	0	0
T4	0	16	0	0
T5	19252	1	0	0
T16	15961	50	0	0
T17	3524	2	0	0
T18	1525	0	0	0
T19	2238	0	0	0
T20	2331	1	0	0
T21	1075	1	0	0
T22	4646	1	0	0
T23	1950	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T16,T21,T22
0	1	Covered	T2,T3,T9
1	0	Covered	T6,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T22,T2
1	0	Covered	T21,T40,T41
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	228857434	3335	0	0
GateOpen_A	228857434	4921	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228857434	3335	0	0
T2	120258	31	0	0
T3	0	8	0	0
T4	50824	0	0	0
T7	1842	0	0	0
T9	0	55	0	0
T10	0	14	0	0
T21	532	1	0	0
T22	2323	1	0	0
T23	975	0	0	0
T26	11259	0	0	0
T27	1565	0	0	0
T28	1813	0	0	0
T29	991	0	0	0
T40	0	2	0	0
T41	0	4	0	0
T59	0	11	0	0
T162	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228857434	4921	0	0
T1	44184	1	0	0
T2	0	34	0	0
T4	0	16	0	0
T5	18266	1	0	0
T16	7980	50	0	0
T17	1788	1	0	0
T18	763	0	0	0
T19	1118	0	0	0
T20	1166	1	0	0
T21	532	2	0	0
T22	2323	1	0	0
T23	975	1	0	0