Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	772992800	69205	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	772992800	69205	0	0
T1	441810	115	0	0
T2	1309675	1382	0	0
T3	0	678	0	0
T9	0	2550	0	0
T10	0	305	0	0
T11	0	39	0	0
T12	0	124	0	0
T13	0	231	0	0
T14	0	211	0	0
T15	0	2258	0	0
T16	79800	0	0	0
T17	4465	0	0	0
T18	7785	0	0	0
T19	5820	0	0	0
T20	11650	0	0	0
T21	5590	0	0	0
T22	6285	0	0	0
T23	9955	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154598560	10106	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	10106	0	0
T1	88362	17	0	0
T2	261935	177	0	0
T3	0	100	0	0
T9	0	367	0	0
T10	0	40	0	0
T11	0	6	0	0
T12	0	20	0	0
T13	0	38	0	0
T14	0	31	0	0
T15	0	340	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154598560	9926	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	9926	0	0
T1	88362	15	0	0
T2	261935	199	0	0
T3	0	84	0	0
T9	0	362	0	0
T10	0	40	0	0
T11	0	6	0	0
T12	0	20	0	0
T13	0	38	0	0
T14	0	30	0	0
T15	0	342	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154598560	13941	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	13941	0	0
T1	88362	23	0	0
T2	261935	275	0	0
T3	0	132	0	0
T9	0	512	0	0
T10	0	62	0	0
T11	0	8	0	0
T12	0	27	0	0
T13	0	47	0	0
T14	0	42	0	0
T15	0	444	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154598560	13948	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	13948	0	0
T1	88362	23	0	0
T2	261935	276	0	0
T3	0	142	0	0
T9	0	511	0	0
T10	0	60	0	0
T11	0	8	0	0
T12	0	24	0	0
T13	0	44	0	0
T14	0	43	0	0
T15	0	452	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	154598560	21284	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	21284	0	0
T1	88362	37	0	0
T2	261935	455	0	0
T3	0	220	0	0
T9	0	798	0	0
T10	0	103	0	0
T11	0	11	0	0
T12	0	33	0	0
T13	0	64	0	0
T14	0	65	0	0
T15	0	680	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0