Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T16 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
T19 |
28 |
28 |
0 |
0 |
T20 |
28 |
28 |
0 |
0 |
T21 |
28 |
28 |
0 |
0 |
T22 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
2352629 |
2349323 |
0 |
0 |
T5 |
946392 |
942632 |
0 |
0 |
T6 |
66741 |
64366 |
0 |
0 |
T16 |
421230 |
196226 |
0 |
0 |
T17 |
56267 |
54802 |
0 |
0 |
T18 |
40983 |
37551 |
0 |
0 |
T19 |
44455 |
41715 |
0 |
0 |
T20 |
62116 |
58356 |
0 |
0 |
T21 |
29100 |
27796 |
0 |
0 |
T22 |
76220 |
74354 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
927591360 |
915120408 |
0 |
14490 |
T1 |
530172 |
529350 |
0 |
18 |
T5 |
228324 |
227376 |
0 |
18 |
T6 |
15126 |
14538 |
0 |
18 |
T16 |
95760 |
40290 |
0 |
18 |
T17 |
5358 |
5184 |
0 |
18 |
T18 |
9342 |
8496 |
0 |
18 |
T19 |
6984 |
6504 |
0 |
18 |
T20 |
13980 |
13074 |
0 |
18 |
T21 |
6708 |
6366 |
0 |
18 |
T22 |
7542 |
7308 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
633278 |
632291 |
0 |
21 |
T5 |
247576 |
246477 |
0 |
21 |
T6 |
17932 |
17236 |
0 |
21 |
T16 |
114380 |
48049 |
0 |
21 |
T17 |
19673 |
19045 |
0 |
21 |
T18 |
10994 |
9999 |
0 |
21 |
T19 |
13885 |
12941 |
0 |
21 |
T20 |
16698 |
15617 |
0 |
21 |
T21 |
7746 |
7348 |
0 |
21 |
T22 |
26516 |
25724 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
192275 |
0 |
0 |
T1 |
368192 |
4 |
0 |
0 |
T2 |
755681 |
79 |
0 |
0 |
T3 |
0 |
78 |
0 |
0 |
T4 |
307056 |
0 |
0 |
0 |
T5 |
152216 |
4 |
0 |
0 |
T6 |
10396 |
103 |
0 |
0 |
T7 |
11282 |
0 |
0 |
0 |
T9 |
0 |
1046 |
0 |
0 |
T10 |
0 |
163 |
0 |
0 |
T12 |
0 |
109 |
0 |
0 |
T16 |
66500 |
8 |
0 |
0 |
T17 |
14364 |
8 |
0 |
0 |
T18 |
6356 |
29 |
0 |
0 |
T19 |
9320 |
12 |
0 |
0 |
T20 |
16698 |
210 |
0 |
0 |
T21 |
7746 |
12 |
0 |
0 |
T22 |
26516 |
16 |
0 |
0 |
T23 |
5932 |
93 |
0 |
0 |
T26 |
28614 |
0 |
0 |
0 |
T27 |
8865 |
163 |
0 |
0 |
T28 |
10875 |
0 |
0 |
0 |
T70 |
0 |
194 |
0 |
0 |
T97 |
0 |
102 |
0 |
0 |
T98 |
0 |
73 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1189179 |
1187643 |
0 |
0 |
T5 |
470492 |
468740 |
0 |
0 |
T6 |
33683 |
32553 |
0 |
0 |
T16 |
211090 |
105898 |
0 |
0 |
T17 |
31236 |
30534 |
0 |
0 |
T18 |
20647 |
19017 |
0 |
0 |
T19 |
23586 |
22231 |
0 |
0 |
T20 |
31438 |
29626 |
0 |
0 |
T21 |
14646 |
14043 |
0 |
0 |
T22 |
42162 |
41283 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T20,T23,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T20,T23,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T20,T23,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T20,T23,T2 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T20,T23,T2 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T20,T23,T2 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T20,T23,T2 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T20,T23,T2 |
0 |
Covered |
T6,T5,T1 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447206114 |
443173907 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
19252 |
19104 |
0 |
0 |
T6 |
2494 |
2401 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
3523 |
3416 |
0 |
0 |
T18 |
1524 |
1390 |
0 |
0 |
T19 |
2237 |
2088 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1074 |
1021 |
0 |
0 |
T22 |
4646 |
4511 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447206114 |
443167144 |
0 |
2415 |
T1 |
88362 |
88225 |
0 |
3 |
T5 |
19252 |
19101 |
0 |
3 |
T6 |
2494 |
2398 |
0 |
3 |
T16 |
15960 |
6715 |
0 |
3 |
T17 |
3523 |
3413 |
0 |
3 |
T18 |
1524 |
1387 |
0 |
3 |
T19 |
2237 |
2085 |
0 |
3 |
T20 |
2330 |
2179 |
0 |
3 |
T21 |
1074 |
1018 |
0 |
3 |
T22 |
4646 |
4508 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447206114 |
27013 |
0 |
0 |
T2 |
231811 |
34 |
0 |
0 |
T3 |
0 |
32 |
0 |
0 |
T4 |
101642 |
0 |
0 |
0 |
T7 |
3684 |
0 |
0 |
0 |
T9 |
0 |
431 |
0 |
0 |
T10 |
0 |
65 |
0 |
0 |
T20 |
2330 |
52 |
0 |
0 |
T21 |
1074 |
0 |
0 |
0 |
T22 |
4646 |
0 |
0 |
0 |
T23 |
1950 |
30 |
0 |
0 |
T26 |
22516 |
0 |
0 |
0 |
T27 |
3129 |
47 |
0 |
0 |
T28 |
3625 |
0 |
0 |
0 |
T70 |
0 |
60 |
0 |
0 |
T97 |
0 |
30 |
0 |
0 |
T98 |
0 |
38 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T20,T23,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T20,T23,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T20,T23,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T20,T23,T2 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T20,T23,T2 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T20,T23,T2 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T20,T23,T2 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T20,T23,T2 |
0 |
Covered |
T6,T5,T1 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152520068 |
0 |
2415 |
T1 |
88362 |
88225 |
0 |
3 |
T5 |
38054 |
37896 |
0 |
3 |
T6 |
2521 |
2423 |
0 |
3 |
T16 |
15960 |
6715 |
0 |
3 |
T17 |
893 |
864 |
0 |
3 |
T18 |
1557 |
1416 |
0 |
3 |
T19 |
1164 |
1084 |
0 |
3 |
T20 |
2330 |
2179 |
0 |
3 |
T21 |
1118 |
1061 |
0 |
3 |
T22 |
1257 |
1218 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
17079 |
0 |
0 |
T2 |
261935 |
29 |
0 |
0 |
T3 |
0 |
21 |
0 |
0 |
T4 |
102707 |
0 |
0 |
0 |
T7 |
3799 |
0 |
0 |
0 |
T9 |
0 |
270 |
0 |
0 |
T10 |
0 |
43 |
0 |
0 |
T12 |
0 |
109 |
0 |
0 |
T20 |
2330 |
31 |
0 |
0 |
T21 |
1118 |
0 |
0 |
0 |
T22 |
1257 |
0 |
0 |
0 |
T23 |
1991 |
29 |
0 |
0 |
T26 |
3049 |
0 |
0 |
0 |
T27 |
2868 |
68 |
0 |
0 |
T28 |
3625 |
0 |
0 |
0 |
T70 |
0 |
74 |
0 |
0 |
T97 |
0 |
41 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T20,T23,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T20,T23,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T20,T23,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T20,T23,T2 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T20,T23,T2 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T20,T23,T2 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T20,T23,T2 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T20,T23,T2 |
0 |
Covered |
T6,T5,T1 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152520068 |
0 |
2415 |
T1 |
88362 |
88225 |
0 |
3 |
T5 |
38054 |
37896 |
0 |
3 |
T6 |
2521 |
2423 |
0 |
3 |
T16 |
15960 |
6715 |
0 |
3 |
T17 |
893 |
864 |
0 |
3 |
T18 |
1557 |
1416 |
0 |
3 |
T19 |
1164 |
1084 |
0 |
3 |
T20 |
2330 |
2179 |
0 |
3 |
T21 |
1118 |
1061 |
0 |
3 |
T22 |
1257 |
1218 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
19481 |
0 |
0 |
T2 |
261935 |
16 |
0 |
0 |
T3 |
0 |
25 |
0 |
0 |
T4 |
102707 |
0 |
0 |
0 |
T7 |
3799 |
0 |
0 |
0 |
T9 |
0 |
345 |
0 |
0 |
T10 |
0 |
55 |
0 |
0 |
T20 |
2330 |
47 |
0 |
0 |
T21 |
1118 |
0 |
0 |
0 |
T22 |
1257 |
0 |
0 |
0 |
T23 |
1991 |
34 |
0 |
0 |
T26 |
3049 |
0 |
0 |
0 |
T27 |
2868 |
48 |
0 |
0 |
T28 |
3625 |
0 |
0 |
0 |
T70 |
0 |
60 |
0 |
0 |
T97 |
0 |
31 |
0 |
0 |
T98 |
0 |
35 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
474590652 |
0 |
0 |
T1 |
92048 |
91979 |
0 |
0 |
T5 |
38054 |
37971 |
0 |
0 |
T6 |
2599 |
2530 |
0 |
0 |
T16 |
16625 |
11431 |
0 |
0 |
T17 |
3591 |
3551 |
0 |
0 |
T18 |
1589 |
1491 |
0 |
0 |
T19 |
2330 |
2218 |
0 |
0 |
T20 |
2427 |
2301 |
0 |
0 |
T21 |
1109 |
1083 |
0 |
0 |
T22 |
4839 |
4798 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
474590652 |
0 |
0 |
T1 |
92048 |
91979 |
0 |
0 |
T5 |
38054 |
37971 |
0 |
0 |
T6 |
2599 |
2530 |
0 |
0 |
T16 |
16625 |
11431 |
0 |
0 |
T17 |
3591 |
3551 |
0 |
0 |
T18 |
1589 |
1491 |
0 |
0 |
T19 |
2330 |
2218 |
0 |
0 |
T20 |
2427 |
2301 |
0 |
0 |
T21 |
1109 |
1083 |
0 |
0 |
T22 |
4839 |
4798 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447206114 |
445172811 |
0 |
0 |
T1 |
88362 |
88296 |
0 |
0 |
T5 |
19252 |
19173 |
0 |
0 |
T6 |
2494 |
2428 |
0 |
0 |
T16 |
15960 |
10995 |
0 |
0 |
T17 |
3523 |
3484 |
0 |
0 |
T18 |
1524 |
1431 |
0 |
0 |
T19 |
2237 |
2129 |
0 |
0 |
T20 |
2330 |
2209 |
0 |
0 |
T21 |
1074 |
1049 |
0 |
0 |
T22 |
4646 |
4607 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447206114 |
445172811 |
0 |
0 |
T1 |
88362 |
88296 |
0 |
0 |
T5 |
19252 |
19173 |
0 |
0 |
T6 |
2494 |
2428 |
0 |
0 |
T16 |
15960 |
10995 |
0 |
0 |
T17 |
3523 |
3484 |
0 |
0 |
T18 |
1524 |
1431 |
0 |
0 |
T19 |
2237 |
2129 |
0 |
0 |
T20 |
2330 |
2209 |
0 |
0 |
T21 |
1074 |
1049 |
0 |
0 |
T22 |
4646 |
4607 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
222886692 |
222886692 |
0 |
0 |
T1 |
44148 |
44148 |
0 |
0 |
T5 |
9587 |
9587 |
0 |
0 |
T6 |
1214 |
1214 |
0 |
0 |
T16 |
5509 |
5509 |
0 |
0 |
T17 |
1742 |
1742 |
0 |
0 |
T18 |
716 |
716 |
0 |
0 |
T19 |
1065 |
1065 |
0 |
0 |
T20 |
1219 |
1219 |
0 |
0 |
T21 |
525 |
525 |
0 |
0 |
T22 |
2304 |
2304 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
222886692 |
222886692 |
0 |
0 |
T1 |
44148 |
44148 |
0 |
0 |
T5 |
9587 |
9587 |
0 |
0 |
T6 |
1214 |
1214 |
0 |
0 |
T16 |
5509 |
5509 |
0 |
0 |
T17 |
1742 |
1742 |
0 |
0 |
T18 |
716 |
716 |
0 |
0 |
T19 |
1065 |
1065 |
0 |
0 |
T20 |
1219 |
1219 |
0 |
0 |
T21 |
525 |
525 |
0 |
0 |
T22 |
2304 |
2304 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111442734 |
111442734 |
0 |
0 |
T1 |
22074 |
22074 |
0 |
0 |
T5 |
4793 |
4793 |
0 |
0 |
T6 |
607 |
607 |
0 |
0 |
T16 |
2756 |
2756 |
0 |
0 |
T17 |
871 |
871 |
0 |
0 |
T18 |
358 |
358 |
0 |
0 |
T19 |
532 |
532 |
0 |
0 |
T20 |
608 |
608 |
0 |
0 |
T21 |
262 |
262 |
0 |
0 |
T22 |
1152 |
1152 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111442734 |
111442734 |
0 |
0 |
T1 |
22074 |
22074 |
0 |
0 |
T5 |
4793 |
4793 |
0 |
0 |
T6 |
607 |
607 |
0 |
0 |
T16 |
2756 |
2756 |
0 |
0 |
T17 |
871 |
871 |
0 |
0 |
T18 |
358 |
358 |
0 |
0 |
T19 |
532 |
532 |
0 |
0 |
T20 |
608 |
608 |
0 |
0 |
T21 |
262 |
262 |
0 |
0 |
T22 |
1152 |
1152 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
228857014 |
227829193 |
0 |
0 |
T1 |
44183 |
44150 |
0 |
0 |
T5 |
18266 |
18226 |
0 |
0 |
T6 |
1247 |
1214 |
0 |
0 |
T16 |
7980 |
5483 |
0 |
0 |
T17 |
1787 |
1768 |
0 |
0 |
T18 |
762 |
715 |
0 |
0 |
T19 |
1118 |
1065 |
0 |
0 |
T20 |
1166 |
1105 |
0 |
0 |
T21 |
532 |
520 |
0 |
0 |
T22 |
2323 |
2304 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
228857014 |
227829193 |
0 |
0 |
T1 |
44183 |
44150 |
0 |
0 |
T5 |
18266 |
18226 |
0 |
0 |
T6 |
1247 |
1214 |
0 |
0 |
T16 |
7980 |
5483 |
0 |
0 |
T17 |
1787 |
1768 |
0 |
0 |
T18 |
762 |
715 |
0 |
0 |
T19 |
1118 |
1065 |
0 |
0 |
T20 |
1166 |
1105 |
0 |
0 |
T21 |
532 |
520 |
0 |
0 |
T22 |
2323 |
2304 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152520068 |
0 |
2415 |
T1 |
88362 |
88225 |
0 |
3 |
T5 |
38054 |
37896 |
0 |
3 |
T6 |
2521 |
2423 |
0 |
3 |
T16 |
15960 |
6715 |
0 |
3 |
T17 |
893 |
864 |
0 |
3 |
T18 |
1557 |
1416 |
0 |
3 |
T19 |
1164 |
1084 |
0 |
3 |
T20 |
2330 |
2179 |
0 |
3 |
T21 |
1118 |
1061 |
0 |
3 |
T22 |
1257 |
1218 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152520068 |
0 |
2415 |
T1 |
88362 |
88225 |
0 |
3 |
T5 |
38054 |
37896 |
0 |
3 |
T6 |
2521 |
2423 |
0 |
3 |
T16 |
15960 |
6715 |
0 |
3 |
T17 |
893 |
864 |
0 |
3 |
T18 |
1557 |
1416 |
0 |
3 |
T19 |
1164 |
1084 |
0 |
3 |
T20 |
2330 |
2179 |
0 |
3 |
T21 |
1118 |
1061 |
0 |
3 |
T22 |
1257 |
1218 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152520068 |
0 |
2415 |
T1 |
88362 |
88225 |
0 |
3 |
T5 |
38054 |
37896 |
0 |
3 |
T6 |
2521 |
2423 |
0 |
3 |
T16 |
15960 |
6715 |
0 |
3 |
T17 |
893 |
864 |
0 |
3 |
T18 |
1557 |
1416 |
0 |
3 |
T19 |
1164 |
1084 |
0 |
3 |
T20 |
2330 |
2179 |
0 |
3 |
T21 |
1118 |
1061 |
0 |
3 |
T22 |
1257 |
1218 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152520068 |
0 |
2415 |
T1 |
88362 |
88225 |
0 |
3 |
T5 |
38054 |
37896 |
0 |
3 |
T6 |
2521 |
2423 |
0 |
3 |
T16 |
15960 |
6715 |
0 |
3 |
T17 |
893 |
864 |
0 |
3 |
T18 |
1557 |
1416 |
0 |
3 |
T19 |
1164 |
1084 |
0 |
3 |
T20 |
2330 |
2179 |
0 |
3 |
T21 |
1118 |
1061 |
0 |
3 |
T22 |
1257 |
1218 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152520068 |
0 |
2415 |
T1 |
88362 |
88225 |
0 |
3 |
T5 |
38054 |
37896 |
0 |
3 |
T6 |
2521 |
2423 |
0 |
3 |
T16 |
15960 |
6715 |
0 |
3 |
T17 |
893 |
864 |
0 |
3 |
T18 |
1557 |
1416 |
0 |
3 |
T19 |
1164 |
1084 |
0 |
3 |
T20 |
2330 |
2179 |
0 |
3 |
T21 |
1118 |
1061 |
0 |
3 |
T22 |
1257 |
1218 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152520068 |
0 |
2415 |
T1 |
88362 |
88225 |
0 |
3 |
T5 |
38054 |
37896 |
0 |
3 |
T6 |
2521 |
2423 |
0 |
3 |
T16 |
15960 |
6715 |
0 |
3 |
T17 |
893 |
864 |
0 |
3 |
T18 |
1557 |
1416 |
0 |
3 |
T19 |
1164 |
1084 |
0 |
3 |
T20 |
2330 |
2179 |
0 |
3 |
T21 |
1118 |
1061 |
0 |
3 |
T22 |
1257 |
1218 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154598560 |
152526990 |
0 |
0 |
T1 |
88362 |
88228 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2521 |
2426 |
0 |
0 |
T16 |
15960 |
6868 |
0 |
0 |
T17 |
893 |
867 |
0 |
0 |
T18 |
1557 |
1419 |
0 |
0 |
T19 |
1164 |
1087 |
0 |
0 |
T20 |
2330 |
2182 |
0 |
0 |
T21 |
1118 |
1064 |
0 |
0 |
T22 |
1257 |
1221 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472485074 |
0 |
0 |
T1 |
92048 |
91907 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2599 |
2501 |
0 |
0 |
T16 |
16625 |
7129 |
0 |
0 |
T17 |
3591 |
3479 |
0 |
0 |
T18 |
1589 |
1448 |
0 |
0 |
T19 |
2330 |
2175 |
0 |
0 |
T20 |
2427 |
2273 |
0 |
0 |
T21 |
1109 |
1055 |
0 |
0 |
T22 |
4839 |
4698 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472478287 |
0 |
2415 |
T1 |
92048 |
91904 |
0 |
3 |
T5 |
38054 |
37896 |
0 |
3 |
T6 |
2599 |
2498 |
0 |
3 |
T16 |
16625 |
6976 |
0 |
3 |
T17 |
3591 |
3476 |
0 |
3 |
T18 |
1589 |
1445 |
0 |
3 |
T19 |
2330 |
2172 |
0 |
3 |
T20 |
2427 |
2270 |
0 |
3 |
T21 |
1109 |
1052 |
0 |
3 |
T22 |
4839 |
4695 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
32252 |
0 |
0 |
T1 |
92048 |
1 |
0 |
0 |
T5 |
38054 |
1 |
0 |
0 |
T6 |
2599 |
25 |
0 |
0 |
T16 |
16625 |
2 |
0 |
0 |
T17 |
3591 |
5 |
0 |
0 |
T18 |
1589 |
9 |
0 |
0 |
T19 |
2330 |
3 |
0 |
0 |
T20 |
2427 |
21 |
0 |
0 |
T21 |
1109 |
5 |
0 |
0 |
T22 |
4839 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472485074 |
0 |
0 |
T1 |
92048 |
91907 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2599 |
2501 |
0 |
0 |
T16 |
16625 |
7129 |
0 |
0 |
T17 |
3591 |
3479 |
0 |
0 |
T18 |
1589 |
1448 |
0 |
0 |
T19 |
2330 |
2175 |
0 |
0 |
T20 |
2427 |
2273 |
0 |
0 |
T21 |
1109 |
1055 |
0 |
0 |
T22 |
4839 |
4698 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472485074 |
0 |
0 |
T1 |
92048 |
91907 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2599 |
2501 |
0 |
0 |
T16 |
16625 |
7129 |
0 |
0 |
T17 |
3591 |
3479 |
0 |
0 |
T18 |
1589 |
1448 |
0 |
0 |
T19 |
2330 |
2175 |
0 |
0 |
T20 |
2427 |
2273 |
0 |
0 |
T21 |
1109 |
1055 |
0 |
0 |
T22 |
4839 |
4698 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472485074 |
0 |
0 |
T1 |
92048 |
91907 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2599 |
2501 |
0 |
0 |
T16 |
16625 |
7129 |
0 |
0 |
T17 |
3591 |
3479 |
0 |
0 |
T18 |
1589 |
1448 |
0 |
0 |
T19 |
2330 |
2175 |
0 |
0 |
T20 |
2427 |
2273 |
0 |
0 |
T21 |
1109 |
1055 |
0 |
0 |
T22 |
4839 |
4698 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472478287 |
0 |
2415 |
T1 |
92048 |
91904 |
0 |
3 |
T5 |
38054 |
37896 |
0 |
3 |
T6 |
2599 |
2498 |
0 |
3 |
T16 |
16625 |
6976 |
0 |
3 |
T17 |
3591 |
3476 |
0 |
3 |
T18 |
1589 |
1445 |
0 |
3 |
T19 |
2330 |
2172 |
0 |
3 |
T20 |
2427 |
2270 |
0 |
3 |
T21 |
1109 |
1052 |
0 |
3 |
T22 |
4839 |
4695 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
32186 |
0 |
0 |
T1 |
92048 |
1 |
0 |
0 |
T5 |
38054 |
1 |
0 |
0 |
T6 |
2599 |
36 |
0 |
0 |
T16 |
16625 |
2 |
0 |
0 |
T17 |
3591 |
1 |
0 |
0 |
T18 |
1589 |
6 |
0 |
0 |
T19 |
2330 |
3 |
0 |
0 |
T20 |
2427 |
13 |
0 |
0 |
T21 |
1109 |
5 |
0 |
0 |
T22 |
4839 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472485074 |
0 |
0 |
T1 |
92048 |
91907 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2599 |
2501 |
0 |
0 |
T16 |
16625 |
7129 |
0 |
0 |
T17 |
3591 |
3479 |
0 |
0 |
T18 |
1589 |
1448 |
0 |
0 |
T19 |
2330 |
2175 |
0 |
0 |
T20 |
2427 |
2273 |
0 |
0 |
T21 |
1109 |
1055 |
0 |
0 |
T22 |
4839 |
4698 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472485074 |
0 |
0 |
T1 |
92048 |
91907 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2599 |
2501 |
0 |
0 |
T16 |
16625 |
7129 |
0 |
0 |
T17 |
3591 |
3479 |
0 |
0 |
T18 |
1589 |
1448 |
0 |
0 |
T19 |
2330 |
2175 |
0 |
0 |
T20 |
2427 |
2273 |
0 |
0 |
T21 |
1109 |
1055 |
0 |
0 |
T22 |
4839 |
4698 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472485074 |
0 |
0 |
T1 |
92048 |
91907 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2599 |
2501 |
0 |
0 |
T16 |
16625 |
7129 |
0 |
0 |
T17 |
3591 |
3479 |
0 |
0 |
T18 |
1589 |
1448 |
0 |
0 |
T19 |
2330 |
2175 |
0 |
0 |
T20 |
2427 |
2273 |
0 |
0 |
T21 |
1109 |
1055 |
0 |
0 |
T22 |
4839 |
4698 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472478287 |
0 |
2415 |
T1 |
92048 |
91904 |
0 |
3 |
T5 |
38054 |
37896 |
0 |
3 |
T6 |
2599 |
2498 |
0 |
3 |
T16 |
16625 |
6976 |
0 |
3 |
T17 |
3591 |
3476 |
0 |
3 |
T18 |
1589 |
1445 |
0 |
3 |
T19 |
2330 |
2172 |
0 |
3 |
T20 |
2427 |
2270 |
0 |
3 |
T21 |
1109 |
1052 |
0 |
3 |
T22 |
4839 |
4695 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
32024 |
0 |
0 |
T1 |
92048 |
1 |
0 |
0 |
T5 |
38054 |
1 |
0 |
0 |
T6 |
2599 |
21 |
0 |
0 |
T16 |
16625 |
2 |
0 |
0 |
T17 |
3591 |
1 |
0 |
0 |
T18 |
1589 |
8 |
0 |
0 |
T19 |
2330 |
3 |
0 |
0 |
T20 |
2427 |
19 |
0 |
0 |
T21 |
1109 |
1 |
0 |
0 |
T22 |
4839 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472485074 |
0 |
0 |
T1 |
92048 |
91907 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2599 |
2501 |
0 |
0 |
T16 |
16625 |
7129 |
0 |
0 |
T17 |
3591 |
3479 |
0 |
0 |
T18 |
1589 |
1448 |
0 |
0 |
T19 |
2330 |
2175 |
0 |
0 |
T20 |
2427 |
2273 |
0 |
0 |
T21 |
1109 |
1055 |
0 |
0 |
T22 |
4839 |
4698 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472485074 |
0 |
0 |
T1 |
92048 |
91907 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2599 |
2501 |
0 |
0 |
T16 |
16625 |
7129 |
0 |
0 |
T17 |
3591 |
3479 |
0 |
0 |
T18 |
1589 |
1448 |
0 |
0 |
T19 |
2330 |
2175 |
0 |
0 |
T20 |
2427 |
2273 |
0 |
0 |
T21 |
1109 |
1055 |
0 |
0 |
T22 |
4839 |
4698 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T5,T1 |
1 | Covered | T6,T5,T1 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T5,T1 |
0 |
Covered |
T6,T5,T1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472485074 |
0 |
0 |
T1 |
92048 |
91907 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2599 |
2501 |
0 |
0 |
T16 |
16625 |
7129 |
0 |
0 |
T17 |
3591 |
3479 |
0 |
0 |
T18 |
1589 |
1448 |
0 |
0 |
T19 |
2330 |
2175 |
0 |
0 |
T20 |
2427 |
2273 |
0 |
0 |
T21 |
1109 |
1055 |
0 |
0 |
T22 |
4839 |
4698 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472478287 |
0 |
2415 |
T1 |
92048 |
91904 |
0 |
3 |
T5 |
38054 |
37896 |
0 |
3 |
T6 |
2599 |
2498 |
0 |
3 |
T16 |
16625 |
6976 |
0 |
3 |
T17 |
3591 |
3476 |
0 |
3 |
T18 |
1589 |
1445 |
0 |
3 |
T19 |
2330 |
2172 |
0 |
3 |
T20 |
2427 |
2270 |
0 |
3 |
T21 |
1109 |
1052 |
0 |
3 |
T22 |
4839 |
4695 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
32240 |
0 |
0 |
T1 |
92048 |
1 |
0 |
0 |
T5 |
38054 |
1 |
0 |
0 |
T6 |
2599 |
21 |
0 |
0 |
T16 |
16625 |
2 |
0 |
0 |
T17 |
3591 |
1 |
0 |
0 |
T18 |
1589 |
6 |
0 |
0 |
T19 |
2330 |
3 |
0 |
0 |
T20 |
2427 |
27 |
0 |
0 |
T21 |
1109 |
1 |
0 |
0 |
T22 |
4839 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472485074 |
0 |
0 |
T1 |
92048 |
91907 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2599 |
2501 |
0 |
0 |
T16 |
16625 |
7129 |
0 |
0 |
T17 |
3591 |
3479 |
0 |
0 |
T18 |
1589 |
1448 |
0 |
0 |
T19 |
2330 |
2175 |
0 |
0 |
T20 |
2427 |
2273 |
0 |
0 |
T21 |
1109 |
1055 |
0 |
0 |
T22 |
4839 |
4698 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
476730956 |
472485074 |
0 |
0 |
T1 |
92048 |
91907 |
0 |
0 |
T5 |
38054 |
37899 |
0 |
0 |
T6 |
2599 |
2501 |
0 |
0 |
T16 |
16625 |
7129 |
0 |
0 |
T17 |
3591 |
3479 |
0 |
0 |
T18 |
1589 |
1448 |
0 |
0 |
T19 |
2330 |
2175 |
0 |
0 |
T20 |
2427 |
2273 |
0 |
0 |
T21 |
1109 |
1055 |
0 |
0 |
T22 |
4839 |
4698 |
0 |
0 |