Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T5,T1
0	1	Unreachable
1	0	Covered	T16,T2,T4

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	154598560	152386045	0	0
AllClkBypReqTrue_A	154598560	138691	0	0
IoClkBypReqFalse_A	154598560	152305646	0	2415
IoClkBypReqTrue_A	154598560	214582	0	0
LcClkBypAckFalse_A	154598560	152398475	0	0
LcClkBypAckTrue_A	154598560	126261	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	152386045	0	0
T1	88362	88227	0	0
T5	38054	37898	0	0
T6	2521	2425	0	0
T16	15960	6817	0	0
T17	893	866	0	0
T18	1557	1418	0	0
T19	1164	1086	0	0
T20	2330	1973	0	0
T21	1118	1063	0	0
T22	1257	1220	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	138691	0	0
T2	261935	120	0	0
T3	0	67	0	0
T4	102707	0	0	0
T7	3799	0	0	0
T9	0	3328	0	0
T10	0	462	0	0
T20	2330	208	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	188	0	0
T26	3049	0	0	0
T27	2868	426	0	0
T28	3625	0	0	0
T70	0	212	0	0
T97	0	155	0	0
T98	0	49	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	152305646	0	2415
T1	88362	88225	0	3
T5	38054	37896	0	3
T6	2521	2423	0	3
T16	15960	6715	0	3
T17	893	864	0	3
T18	1557	1416	0	3
T19	1164	1084	0	3
T20	2330	1932	0	3
T21	1118	1061	0	3
T22	1257	1218	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	214582	0	0
T2	261935	431	0	0
T3	0	162	0	0
T4	102707	0	0	0
T7	3799	0	0	0
T9	0	4132	0	0
T10	0	635	0	0
T12	0	1060	0	0
T20	2330	247	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	235	0	0
T26	3049	0	0	0
T27	2868	563	0	0
T28	3625	0	0	0
T70	0	404	0	0
T97	0	199	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	152398475	0	0
T1	88362	88227	0	0
T5	38054	37898	0	0
T6	2521	2425	0	0
T16	15960	6817	0	0
T17	893	866	0	0
T18	1557	1418	0	0
T19	1164	1086	0	0
T20	2330	2011	0	0
T21	1118	1063	0	0
T22	1257	1220	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	126261	0	0
T2	261935	202	0	0
T3	0	107	0	0
T4	102707	0	0	0
T7	3799	0	0	0
T9	0	2904	0	0
T10	0	385	0	0
T12	0	541	0	0
T20	2330	170	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	128	0	0
T26	3049	0	0	0
T27	2868	288	0	0
T28	3625	0	0	0
T70	0	138	0	0
T97	0	71	0	0