Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1906925572	15327	0	0
TransStop_A	1906925572	7724	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1906925572	15327	0	0
T1	368192	0	0	0
T2	0	100	0	0
T5	152220	0	0	0
T6	10396	23	0	0
T16	66504	0	0	0
T17	14368	0	0	0
T18	6356	4	0	0
T19	9324	0	0	0
T20	9712	0	0	0
T21	4440	0	0	0
T22	19360	4	0	0
T28	0	36	0	0
T30	0	25	0	0
T31	0	8	0	0
T32	0	33	0	0
T99	0	34	0	0
T100	0	8	0	0
T101	0	13	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1906925572	7724	0	0
T1	368192	0	0	0
T2	0	52	0	0
T5	152220	0	0	0
T6	10396	17	0	0
T9	0	36	0	0
T16	66504	0	0	0
T17	14368	0	0	0
T18	6356	2	0	0
T19	9324	0	0	0
T20	9712	0	0	0
T21	4440	0	0	0
T22	19360	4	0	0
T28	0	16	0	0
T30	0	15	0	0
T31	0	7	0	0
T32	0	18	0	0
T99	0	19	0	0
T100	0	1	0	0
T101	0	13	0	0
T102	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	476731393	3855	0	0
TransStop_A	476731393	1930	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476731393	3855	0	0
T1	92048	0	0	0
T2	0	23	0	0
T5	38055	0	0	0
T6	2599	5	0	0
T16	16626	0	0	0
T17	3592	0	0	0
T18	1589	0	0	0
T19	2331	0	0	0
T20	2428	0	0	0
T21	1110	0	0	0
T22	4840	1	0	0
T28	0	9	0	0
T30	0	9	0	0
T31	0	4	0	0
T32	0	7	0	0
T99	0	9	0	0
T100	0	4	0	0
T101	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476731393	1930	0	0
T1	92048	0	0	0
T2	0	13	0	0
T5	38055	0	0	0
T6	2599	2	0	0
T16	16626	0	0	0
T17	3592	0	0	0
T18	1589	0	0	0
T19	2331	0	0	0
T20	2428	0	0	0
T21	1110	0	0	0
T22	4840	1	0	0
T28	0	6	0	0
T30	0	5	0	0
T31	0	3	0	0
T32	0	5	0	0
T99	0	5	0	0
T100	0	1	0	0
T101	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	476731393	3836	0	0
TransStop_A	476731393	1955	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476731393	3836	0	0
T1	92048	0	0	0
T2	0	25	0	0
T5	38055	0	0	0
T6	2599	7	0	0
T16	16626	0	0	0
T17	3592	0	0	0
T18	1589	1	0	0
T19	2331	0	0	0
T20	2428	0	0	0
T21	1110	0	0	0
T22	4840	1	0	0
T28	0	10	0	0
T30	0	5	0	0
T31	0	2	0	0
T32	0	9	0	0
T99	0	8	0	0
T100	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476731393	1955	0	0
T1	92048	0	0	0
T2	0	14	0	0
T5	38055	0	0	0
T6	2599	5	0	0
T16	16626	0	0	0
T17	3592	0	0	0
T18	1589	1	0	0
T19	2331	0	0	0
T20	2428	0	0	0
T21	1110	0	0	0
T22	4840	1	0	0
T28	0	4	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	4	0	0
T99	0	4	0	0
T101	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	476731393	3840	0	0
TransStop_A	476731393	1919	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476731393	3840	0	0
T1	92048	0	0	0
T2	0	26	0	0
T5	38055	0	0	0
T6	2599	7	0	0
T16	16626	0	0	0
T17	3592	0	0	0
T18	1589	2	0	0
T19	2331	0	0	0
T20	2428	0	0	0
T21	1110	0	0	0
T22	4840	1	0	0
T28	0	9	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	9	0	0
T99	0	8	0	0
T100	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476731393	1919	0	0
T1	92048	0	0	0
T2	0	14	0	0
T5	38055	0	0	0
T6	2599	6	0	0
T16	16626	0	0	0
T17	3592	0	0	0
T18	1589	1	0	0
T19	2331	0	0	0
T20	2428	0	0	0
T21	1110	0	0	0
T22	4840	1	0	0
T28	0	3	0	0
T30	0	1	0	0
T31	0	2	0	0
T32	0	5	0	0
T99	0	4	0	0
T101	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	476731393	3796	0	0
TransStop_A	476731393	1920	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476731393	3796	0	0
T1	92048	0	0	0
T2	0	26	0	0
T5	38055	0	0	0
T6	2599	4	0	0
T16	16626	0	0	0
T17	3592	0	0	0
T18	1589	1	0	0
T19	2331	0	0	0
T20	2428	0	0	0
T21	1110	0	0	0
T22	4840	1	0	0
T28	0	8	0	0
T30	0	9	0	0
T32	0	8	0	0
T99	0	9	0	0
T100	0	1	0	0
T101	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476731393	1920	0	0
T1	92048	0	0	0
T2	0	11	0	0
T5	38055	0	0	0
T6	2599	4	0	0
T9	0	36	0	0
T16	16626	0	0	0
T17	3592	0	0	0
T18	1589	0	0	0
T19	2331	0	0	0
T20	2428	0	0	0
T21	1110	0	0	0
T22	4840	1	0	0
T28	0	3	0	0
T30	0	6	0	0
T32	0	4	0	0
T99	0	6	0	0
T101	0	3	0	0
T102	0	7	0	0