Module Definition
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Module : prim_subreg
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val 95.24 85.71 100.00 100.00
tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val 95.24 85.71 100.00 100.00
tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val 95.24 85.71 100.00 100.00
tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val 95.24 85.71 100.00 100.00
tb.dut.u_reg.u_extclk_ctrl_regwen 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_extclk_ctrl_sel 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_jitter_regwen 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_jitter_enable 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_peri_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_usb_peri_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_aes_hint 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_measure_ctrl_regwen 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.staged_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.shadow_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.committed_reg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_shadow_update_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_measure_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div2_measure_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div4_measure_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_main_measure_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_usb_measure_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_timeout_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div2_timeout_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div4_timeout_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_main_timeout_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_recov_err_code_usb_timeout_err 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fatal_err_code_reg_intg 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fatal_err_code_idle_cnt 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fatal_err_code_shadow_storage_err 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Cond Coverage for Module : prim_subreg ( parameter DW=10,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.committed_reg

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT6,T5,T1
1CoveredT5,T1,T2

Cond Coverage for Module : prim_subreg ( parameter DW=9,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.committed_reg

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT6,T5,T1
1CoveredT5,T1,T2

Cond Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.committed_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.staged_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.shadow_reg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.committed_reg

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT6,T5,T1
1CoveredT5,T1,T2

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=5,RESVAL=1,Mubi=0 + DW=1,SwAccess=0,RESVAL=1,Mubi=0 + DW=1,SwAccess=1,RESVAL,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_extclk_ctrl_regwen

SCORECOND
100.00 100.00
tb.dut.u_reg.u_jitter_regwen

SCORECOND
100.00 100.00
tb.dut.u_reg.u_measure_ctrl_regwen

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_io_peri_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_enables_clk_usb_peri_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_aes_hint

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint

SCORECOND
100.00 100.00
tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint

SCORECOND
95.24 100.00
tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val

SCORECOND
95.24 100.00
tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val

SCORECOND
95.24 100.00
tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val

SCORECOND
95.24 100.00
tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fatal_err_code_reg_intg

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fatal_err_code_idle_cnt

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fatal_err_code_shadow_storage_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_shadow_update_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_measure_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div2_measure_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div4_measure_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_main_measure_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_usb_measure_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_timeout_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div2_timeout_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_io_div4_timeout_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_main_timeout_err

SCORECOND
100.00 100.00
tb.dut.u_reg.u_recov_err_code_usb_timeout_err

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT6,T5,T1
1CoveredT6,T20,T23

Cond Coverage for Module : prim_subreg ( parameter DW=4,SwAccess=0,RESVAL=9,Mubi=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_extclk_ctrl_sel

SCORECOND
100.00 100.00
tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel

SCORECOND
100.00 100.00
tb.dut.u_reg.u_jitter_enable

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_en

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT6,T5,T1
1CoveredT5,T1,T20

Branch Coverage for Module : prim_subreg
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T20,T23,T2
0 Covered T6,T5,T1


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T6,T5,T1
0 1 Covered T20,T23,T2
0 0 Covered T6,T5,T1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%