Unified Coverage Report :: Module :: prim_subreg

Module : prim_subreg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_extclk_ctrl_regwen	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_extclk_ctrl_sel	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_jitter_regwen	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_jitter_enable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_enables_clk_io_peri_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_enables_clk_usb_peri_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_hints_clk_main_aes_hint	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_measure_ctrl_regwen	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.staged_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.shadow_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.committed_reg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_recov_err_code_shadow_update_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_recov_err_code_io_measure_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_recov_err_code_io_div2_measure_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_recov_err_code_io_div4_measure_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_recov_err_code_main_measure_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_recov_err_code_usb_measure_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_recov_err_code_io_timeout_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_recov_err_code_io_div2_timeout_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_recov_err_code_io_div4_timeout_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_recov_err_code_main_timeout_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_recov_err_code_usb_timeout_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fatal_err_code_reg_intg	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fatal_err_code_idle_cnt	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fatal_err_code_shadow_storage_err	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Module : prim_subreg ( parameter DW=10,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.committed_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T6,T5,T1
1	Covered	T5,T1,T2

---

Cond Coverage for Module : prim_subreg ( parameter DW=9,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.committed_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T6,T5,T1
1	Covered	T5,T1,T2

---

Cond Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.committed_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T6,T5,T1
1	Covered	T5,T1,T2

---

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=5,RESVAL=1,Mubi=0 + DW=1,SwAccess=0,RESVAL=1,Mubi=0 + DW=1,SwAccess=1,RESVAL,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_extclk_ctrl_regwen

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_jitter_regwen

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_measure_ctrl_regwen

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_enables_clk_io_peri_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_enables_clk_usb_peri_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_hints_clk_main_aes_hint

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fatal_err_code_reg_intg

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fatal_err_code_idle_cnt

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fatal_err_code_shadow_storage_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_shadow_update_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_measure_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_div2_measure_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_div4_measure_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_main_measure_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_usb_measure_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_timeout_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_div2_timeout_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_div4_timeout_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_main_timeout_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_usb_timeout_err

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T6,T5,T1
1	Covered	T6,T20,T23

---

Cond Coverage for Module : prim_subreg ( parameter DW=4,SwAccess=0,RESVAL=9,Mubi=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_extclk_ctrl_sel

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_jitter_enable

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_en

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T6,T5,T1
1	Covered	T5,T1,T20

---

Branch Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T23,T2
0	Covered	T6,T5,T1

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T5,T1
0	1	Covered	T20,T23,T2
0	0	Covered	T6,T5,T1