Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	154598560	16174097	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	16174097	0	57
T1	88362	12600	0	1
T2	261935	440895	0	0
T3	0	82613	0	0
T9	0	103721	0	0
T10	0	34811	0	0
T11	0	3822	0	1
T12	0	10395	0	1
T13	0	15053	0	0
T16	15960	0	0	0
T17	893	0	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T24	0	1021	0	1
T26	0	642	0	1
T36	0	0	0	1
T103	0	0	0	1
T104	0	0	0	1
T105	0	0	0	1
T106	0	0	0	1