Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	155507539	4801045	0	0
clk_enables_rd_A	155507539	47979	0	0
clk_hints_rd_A	155507539	42660	0	0
extclk_ctrl_rd_A	155507539	52776	0	0
extclk_ctrl_regwen_rd_A	155507539	39288	0	0
jitter_enable_rd_A	155507539	59122	0	0
jitter_regwen_rd_A	155507539	44556	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	4801045	0	0
T2	261935	87254	0	0
T4	102707	0	0	0
T7	3799	0	0	0
T9	0	141807	0	0
T13	0	79914	0	0
T14	0	47655	0	0
T15	0	97769	0	0
T25	0	127638	0	0
T26	3049	0	0	0
T27	2868	0	0	0
T28	3625	0	0	0
T29	2064	0	0	0
T30	2433	0	0	0
T31	986	0	0	0
T32	3348	0	0	0
T55	0	48692	0	0
T56	0	57188	0	0
T57	0	153351	0	0
T58	0	161669	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	47979	0	0
T10	783884	18	0	0
T11	19795	0	0	0
T15	0	3845	0	0
T24	90111	0	0	0
T55	0	1051	0	0
T56	0	2064	0	0
T70	2565	0	0	0
T98	2383	0	0	0
T124	0	1	0	0
T125	0	9	0	0
T126	0	10	0	0
T127	0	1593	0	0
T128	0	4479	0	0
T129	0	1	0	0
T130	1214	0	0	0
T131	1527	0	0	0
T132	49843	0	0	0
T133	683	0	0	0
T134	1153	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	42660	0	0
T10	783884	4	0	0
T11	19795	0	0	0
T15	0	3500	0	0
T24	90111	0	0	0
T55	0	881	0	0
T56	0	1898	0	0
T70	2565	0	0	0
T98	2383	0	0	0
T124	0	3	0	0
T125	0	7	0	0
T126	0	13	0	0
T127	0	1468	0	0
T128	0	3966	0	0
T129	0	1	0	0
T130	1214	0	0	0
T131	1527	0	0	0
T132	49843	0	0	0
T133	683	0	0	0
T134	1153	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	52776	0	0
T7	3799	0	0	0
T10	0	69	0	0
T15	0	4287	0	0
T27	2868	37	0	0
T28	3625	0	0	0
T29	2064	0	0	0
T30	2433	0	0	0
T31	986	0	0	0
T32	3348	0	0	0
T33	97733	0	0	0
T55	0	1134	0	0
T56	0	2419	0	0
T99	2956	0	0	0
T100	1468	0	0	0
T135	0	68	0	0
T136	0	13	0	0
T137	0	4	0	0
T138	0	39	0	0
T139	0	10	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	39288	0	0
T15	344556	3238	0	0
T55	0	773	0	0
T56	0	1669	0	0
T95	0	37	0	0
T127	0	1325	0	0
T128	0	4047	0	0
T140	0	33	0	0
T141	0	13	0	0
T142	0	66	0	0
T143	0	1648	0	0
T144	1191	0	0	0
T145	1091	0	0	0
T146	931	0	0	0
T147	1826	0	0	0
T148	2361	0	0	0
T149	1503	0	0	0
T150	1080	0	0	0
T151	1224	0	0	0
T152	1348	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	59122	0	0
T10	783884	203	0	0
T11	19795	0	0	0
T15	0	5129	0	0
T24	90111	0	0	0
T55	0	876	0	0
T56	0	2000	0	0
T70	2565	0	0	0
T98	2383	0	0	0
T124	0	111	0	0
T125	0	57	0	0
T126	0	169	0	0
T127	0	1695	0	0
T128	0	5389	0	0
T129	0	145	0	0
T130	1214	0	0	0
T131	1527	0	0	0
T132	49843	0	0	0
T133	683	0	0	0
T134	1153	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155507539	44556	0	0
T15	344556	3895	0	0
T55	0	924	0	0
T56	0	1919	0	0
T127	0	1554	0	0
T128	0	4376	0	0
T143	0	1859	0	0
T144	1191	0	0	0
T145	1091	0	0	0
T146	931	0	0	0
T147	1826	0	0	0
T148	2361	0	0	0
T149	1503	0	0	0
T150	1080	0	0	0
T151	1224	0	0	0
T152	1348	0	0	0
T153	0	4956	0	0
T154	0	4590	0	0
T155	0	2403	0	0
T156	0	4727	0	0