SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T6,T16,T18 |
1 | 0 | Covered | T20,T23,T2 |
1 | 1 | Covered | T20,T23,T2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 447206562 | 4393 | 0 | 0 |
g_div2.Div2Whole_A | 447206562 | 5114 | 0 | 0 |
g_div4.Div4Stepped_A | 222887096 | 4331 | 0 | 0 |
g_div4.Div4Whole_A | 222887096 | 4871 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 447206562 | 4393 | 0 | 0 |
T2 | 231811 | 4 | 0 | 0 |
T3 | 0 | 4 | 0 | 0 |
T4 | 101642 | 0 | 0 | 0 |
T7 | 3684 | 0 | 0 | 0 |
T9 | 0 | 84 | 0 | 0 |
T10 | 0 | 10 | 0 | 0 |
T12 | 0 | 25 | 0 | 0 |
T20 | 2331 | 7 | 0 | 0 |
T21 | 1075 | 0 | 0 | 0 |
T22 | 4646 | 0 | 0 | 0 |
T23 | 1950 | 5 | 0 | 0 |
T26 | 22516 | 0 | 0 | 0 |
T27 | 3129 | 9 | 0 | 0 |
T28 | 3626 | 0 | 0 | 0 |
T70 | 0 | 8 | 0 | 0 |
T97 | 0 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 447206562 | 5114 | 0 | 0 |
T2 | 231811 | 6 | 0 | 0 |
T3 | 0 | 6 | 0 | 0 |
T4 | 101642 | 0 | 0 | 0 |
T7 | 3684 | 0 | 0 | 0 |
T9 | 0 | 89 | 0 | 0 |
T10 | 0 | 12 | 0 | 0 |
T20 | 2331 | 12 | 0 | 0 |
T21 | 1075 | 0 | 0 | 0 |
T22 | 4646 | 0 | 0 | 0 |
T23 | 1950 | 5 | 0 | 0 |
T26 | 22516 | 0 | 0 | 0 |
T27 | 3129 | 11 | 0 | 0 |
T28 | 3626 | 0 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T97 | 0 | 7 | 0 | 0 |
T98 | 0 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222887096 | 4331 | 0 | 0 |
T2 | 115452 | 4 | 0 | 0 |
T3 | 0 | 3 | 0 | 0 |
T4 | 25133 | 0 | 0 | 0 |
T7 | 1083 | 0 | 0 | 0 |
T9 | 0 | 84 | 0 | 0 |
T10 | 0 | 10 | 0 | 0 |
T12 | 0 | 25 | 0 | 0 |
T20 | 1219 | 7 | 0 | 0 |
T21 | 525 | 0 | 0 | 0 |
T22 | 2304 | 0 | 0 | 0 |
T23 | 1086 | 5 | 0 | 0 |
T26 | 11246 | 0 | 0 | 0 |
T27 | 1734 | 9 | 0 | 0 |
T28 | 1801 | 0 | 0 | 0 |
T70 | 0 | 8 | 0 | 0 |
T97 | 0 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222887096 | 4871 | 0 | 0 |
T2 | 115452 | 6 | 0 | 0 |
T3 | 0 | 5 | 0 | 0 |
T4 | 25133 | 0 | 0 | 0 |
T7 | 1083 | 0 | 0 | 0 |
T9 | 0 | 89 | 0 | 0 |
T10 | 0 | 11 | 0 | 0 |
T20 | 1219 | 10 | 0 | 0 |
T21 | 525 | 0 | 0 | 0 |
T22 | 2304 | 0 | 0 | 0 |
T23 | 1086 | 4 | 0 | 0 |
T26 | 11246 | 0 | 0 | 0 |
T27 | 1734 | 10 | 0 | 0 |
T28 | 1801 | 0 | 0 | 0 |
T70 | 0 | 6 | 0 | 0 |
T97 | 0 | 7 | 0 | 0 |
T98 | 0 | 4 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T6,T16,T18 |
1 | 0 | Covered | T20,T23,T2 |
1 | 1 | Covered | T20,T23,T2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 447206562 | 4393 | 0 | 0 |
g_div2.Div2Whole_A | 447206562 | 5114 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 447206562 | 4393 | 0 | 0 |
T2 | 231811 | 4 | 0 | 0 |
T3 | 0 | 4 | 0 | 0 |
T4 | 101642 | 0 | 0 | 0 |
T7 | 3684 | 0 | 0 | 0 |
T9 | 0 | 84 | 0 | 0 |
T10 | 0 | 10 | 0 | 0 |
T12 | 0 | 25 | 0 | 0 |
T20 | 2331 | 7 | 0 | 0 |
T21 | 1075 | 0 | 0 | 0 |
T22 | 4646 | 0 | 0 | 0 |
T23 | 1950 | 5 | 0 | 0 |
T26 | 22516 | 0 | 0 | 0 |
T27 | 3129 | 9 | 0 | 0 |
T28 | 3626 | 0 | 0 | 0 |
T70 | 0 | 8 | 0 | 0 |
T97 | 0 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 447206562 | 5114 | 0 | 0 |
T2 | 231811 | 6 | 0 | 0 |
T3 | 0 | 6 | 0 | 0 |
T4 | 101642 | 0 | 0 | 0 |
T7 | 3684 | 0 | 0 | 0 |
T9 | 0 | 89 | 0 | 0 |
T10 | 0 | 12 | 0 | 0 |
T20 | 2331 | 12 | 0 | 0 |
T21 | 1075 | 0 | 0 | 0 |
T22 | 4646 | 0 | 0 | 0 |
T23 | 1950 | 5 | 0 | 0 |
T26 | 22516 | 0 | 0 | 0 |
T27 | 3129 | 11 | 0 | 0 |
T28 | 3626 | 0 | 0 | 0 |
T70 | 0 | 10 | 0 | 0 |
T97 | 0 | 7 | 0 | 0 |
T98 | 0 | 4 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T6,T16,T18 |
1 | 0 | Covered | T20,T23,T2 |
1 | 1 | Covered | T20,T23,T2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 222887096 | 4331 | 0 | 0 |
g_div4.Div4Whole_A | 222887096 | 4871 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222887096 | 4331 | 0 | 0 |
T2 | 115452 | 4 | 0 | 0 |
T3 | 0 | 3 | 0 | 0 |
T4 | 25133 | 0 | 0 | 0 |
T7 | 1083 | 0 | 0 | 0 |
T9 | 0 | 84 | 0 | 0 |
T10 | 0 | 10 | 0 | 0 |
T12 | 0 | 25 | 0 | 0 |
T20 | 1219 | 7 | 0 | 0 |
T21 | 525 | 0 | 0 | 0 |
T22 | 2304 | 0 | 0 | 0 |
T23 | 1086 | 5 | 0 | 0 |
T26 | 11246 | 0 | 0 | 0 |
T27 | 1734 | 9 | 0 | 0 |
T28 | 1801 | 0 | 0 | 0 |
T70 | 0 | 8 | 0 | 0 |
T97 | 0 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 222887096 | 4871 | 0 | 0 |
T2 | 115452 | 6 | 0 | 0 |
T3 | 0 | 5 | 0 | 0 |
T4 | 25133 | 0 | 0 | 0 |
T7 | 1083 | 0 | 0 | 0 |
T9 | 0 | 89 | 0 | 0 |
T10 | 0 | 11 | 0 | 0 |
T20 | 1219 | 10 | 0 | 0 |
T21 | 525 | 0 | 0 | 0 |
T22 | 2304 | 0 | 0 | 0 |
T23 | 1086 | 4 | 0 | 0 |
T26 | 11246 | 0 | 0 | 0 |
T27 | 1734 | 10 | 0 | 0 |
T28 | 1801 | 0 | 0 | 0 |
T70 | 0 | 6 | 0 | 0 |
T97 | 0 | 7 | 0 | 0 |
T98 | 0 | 4 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |