Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	463795680	384	0	0
StatusRise_A	463795680	384	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463795680	384	0	0
T2	785805	0	0	0
T4	308121	0	0	0
T7	3799	0	0	0
T17	1786	2	0	0
T18	3114	0	0	0
T19	2328	0	0	0
T20	4660	0	0	0
T21	3354	2	0	0
T22	3771	0	0	0
T23	5973	0	0	0
T26	9147	0	0	0
T27	2868	0	0	0
T28	3625	0	0	0
T29	2064	0	0	0
T40	0	10	0	0
T41	0	10	0	0
T133	0	5	0	0
T150	0	12	0	0
T157	0	11	0	0
T158	0	14	0	0
T159	0	8	0	0
T160	0	5	0	0
T161	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463795680	384	0	0
T2	785805	0	0	0
T4	308121	0	0	0
T7	3799	0	0	0
T17	1786	2	0	0
T18	3114	0	0	0
T19	2328	0	0	0
T20	4660	0	0	0
T21	3354	2	0	0
T22	3771	0	0	0
T23	5973	0	0	0
T26	9147	0	0	0
T27	2868	0	0	0
T28	3625	0	0	0
T29	2064	0	0	0
T40	0	10	0	0
T41	0	10	0	0
T133	0	5	0	0
T150	0	12	0	0
T157	0	11	0	0
T158	0	14	0	0
T159	0	8	0	0
T160	0	5	0	0
T161	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	154598560	127	0	0
StatusRise_A	154598560	127	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	127	0	0
T2	261935	0	0	0
T4	102707	0	0	0
T17	893	1	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	1	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	3049	0	0	0
T40	0	3	0	0
T41	0	2	0	0
T133	0	2	0	0
T150	0	4	0	0
T157	0	4	0	0
T158	0	4	0	0
T159	0	2	0	0
T160	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	127	0	0
T2	261935	0	0	0
T4	102707	0	0	0
T17	893	1	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	1	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	3049	0	0	0
T40	0	3	0	0
T41	0	2	0	0
T133	0	2	0	0
T150	0	4	0	0
T157	0	4	0	0
T158	0	4	0	0
T159	0	2	0	0
T160	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	154598560	128	0	0
StatusRise_A	154598560	128	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	128	0	0
T2	261935	0	0	0
T4	102707	0	0	0
T17	893	1	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	3049	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T133	0	1	0	0
T150	0	4	0	0
T157	0	3	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	128	0	0
T2	261935	0	0	0
T4	102707	0	0	0
T17	893	1	0	0
T18	1557	0	0	0
T19	1164	0	0	0
T20	2330	0	0	0
T21	1118	0	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	3049	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T133	0	1	0	0
T150	0	4	0	0
T157	0	3	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	154598560	129	0	0
StatusRise_A	154598560	129	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	129	0	0
T2	261935	0	0	0
T4	102707	0	0	0
T7	3799	0	0	0
T21	1118	1	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	3049	0	0	0
T27	2868	0	0	0
T28	3625	0	0	0
T29	2064	0	0	0
T40	0	2	0	0
T41	0	4	0	0
T133	0	2	0	0
T150	0	4	0	0
T157	0	4	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	1	0	0
T161	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154598560	129	0	0
T2	261935	0	0	0
T4	102707	0	0	0
T7	3799	0	0	0
T21	1118	1	0	0
T22	1257	0	0	0
T23	1991	0	0	0
T26	3049	0	0	0
T27	2868	0	0	0
T28	3625	0	0	0
T29	2064	0	0	0
T40	0	2	0	0
T41	0	4	0	0
T133	0	2	0	0
T150	0	4	0	0
T157	0	4	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	1	0	0
T161	0	3	0	0