Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T21
1	0	Covered	T6,T5,T1
1	1	Covered	T6,T5,T1

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	46433	0	0
CgEnOn_A	2147483647	37416	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46433	0	0
T1	566959	3	0	0
T2	2700374	23	0	0
T4	427056	0	0	0
T5	204114	3	0	0
T6	15958	8	0	0
T7	1841	0	0	0
T16	98705	153	0	0
T17	37347	12	0	0
T18	16208	3	0	0
T19	23830	3	0	0
T20	25258	3	0	0
T21	11964	4	0	0
T22	52188	7	0	0
T23	9696	0	0	0
T26	108800	0	0	0
T27	1565	0	0	0
T28	1812	9	0	0
T29	990	0	0	0
T40	0	25	0	0
T41	0	20	0	0
T133	0	5	0	0
T150	0	20	0	0
T157	0	15	0	0
T158	0	20	0	0
T159	0	15	0	0
T160	0	10	0	0
T161	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37416	0	0
T1	368192	0	0	0
T2	3745156	172	0	0
T3	0	38	0	0
T4	617220	0	0	0
T5	152216	0	0	0
T6	10396	5	0	0
T7	3682	0	0	0
T9	0	309	0	0
T10	0	56	0	0
T16	66500	0	0	0
T17	35560	9	0	0
T18	15446	0	0	0
T19	22712	0	0	0
T20	24092	0	0	0
T21	11964	1	0	0
T22	52188	4	0	0
T23	14246	0	0	0
T26	159444	0	0	0
T27	3130	0	0	0
T28	3624	9	0	0
T29	1980	0	0	0
T30	0	9	0	0
T40	0	40	0	0
T41	0	32	0	0
T59	0	51	0	0
T133	0	5	0	0
T150	0	20	0	0
T157	0	15	0	0
T158	0	20	0	0
T159	0	15	0	0
T160	0	10	0	0
T161	0	15	0	0
T162	0	46	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T2
1	0	Unreachable
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	222886692	135	0	0
CgEnOn_A	222886692	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222886692	135	0	0
T2	115452	0	0	0
T4	25133	0	0	0
T17	1742	1	0	0
T18	716	0	0	0
T19	1065	0	0	0
T20	1219	0	0	0
T21	525	0	0	0
T22	2304	0	0	0
T23	1085	0	0	0
T26	11246	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T133	0	1	0	0
T150	0	4	0	0
T157	0	3	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222886692	135	0	0
T2	115452	0	0	0
T4	25133	0	0	0
T17	1742	1	0	0
T18	716	0	0	0
T19	1065	0	0	0
T20	1219	0	0	0
T21	525	0	0	0
T22	2304	0	0	0
T23	1085	0	0	0
T26	11246	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T133	0	1	0	0
T150	0	4	0	0
T157	0	3	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T2
1	0	Unreachable
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	111442734	135	0	0
CgEnOn_A	111442734	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111442734	135	0	0
T2	577261	0	0	0
T4	12566	0	0	0
T17	871	1	0	0
T18	358	0	0	0
T19	532	0	0	0
T20	608	0	0	0
T21	262	0	0	0
T22	1152	0	0	0
T23	541	0	0	0
T26	5623	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T133	0	1	0	0
T150	0	4	0	0
T157	0	3	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111442734	135	0	0
T2	577261	0	0	0
T4	12566	0	0	0
T17	871	1	0	0
T18	358	0	0	0
T19	532	0	0	0
T20	608	0	0	0
T21	262	0	0	0
T22	1152	0	0	0
T23	541	0	0	0
T26	5623	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T133	0	1	0	0
T150	0	4	0	0
T157	0	3	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T2
1	0	Unreachable
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	111442734	135	0	0
CgEnOn_A	111442734	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111442734	135	0	0
T2	577261	0	0	0
T4	12566	0	0	0
T17	871	1	0	0
T18	358	0	0	0
T19	532	0	0	0
T20	608	0	0	0
T21	262	0	0	0
T22	1152	0	0	0
T23	541	0	0	0
T26	5623	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T133	0	1	0	0
T150	0	4	0	0
T157	0	3	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111442734	135	0	0
T2	577261	0	0	0
T4	12566	0	0	0
T17	871	1	0	0
T18	358	0	0	0
T19	532	0	0	0
T20	608	0	0	0
T21	262	0	0	0
T22	1152	0	0	0
T23	541	0	0	0
T26	5623	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T133	0	1	0	0
T150	0	4	0	0
T157	0	3	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T2
1	0	Unreachable
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	111442734	135	0	0
CgEnOn_A	111442734	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111442734	135	0	0
T2	577261	0	0	0
T4	12566	0	0	0
T17	871	1	0	0
T18	358	0	0	0
T19	532	0	0	0
T20	608	0	0	0
T21	262	0	0	0
T22	1152	0	0	0
T23	541	0	0	0
T26	5623	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T133	0	1	0	0
T150	0	4	0	0
T157	0	3	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111442734	135	0	0
T2	577261	0	0	0
T4	12566	0	0	0
T17	871	1	0	0
T18	358	0	0	0
T19	532	0	0	0
T20	608	0	0	0
T21	262	0	0	0
T22	1152	0	0	0
T23	541	0	0	0
T26	5623	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T133	0	1	0	0
T150	0	4	0	0
T157	0	3	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T2
1	0	Unreachable
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	447206114	135	0	0
CgEnOn_A	447206114	128	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447206114	135	0	0
T2	231811	0	0	0
T4	101642	0	0	0
T17	3523	1	0	0
T18	1524	0	0	0
T19	2237	0	0	0
T20	2330	0	0	0
T21	1074	0	0	0
T22	4646	0	0	0
T23	1950	0	0	0
T26	22516	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T133	0	1	0	0
T150	0	4	0	0
T157	0	3	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447206114	128	0	0
T2	231811	0	0	0
T4	101642	0	0	0
T17	3523	1	0	0
T18	1524	0	0	0
T19	2237	0	0	0
T20	2330	0	0	0
T21	1074	0	0	0
T22	4646	0	0	0
T23	1950	0	0	0
T26	22516	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T133	0	1	0	0
T150	0	4	0	0
T157	0	3	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T21
1	0	Unreachable
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	476730956	129	0	0
CgEnOn_A	476730956	128	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476730956	129	0	0
T2	250535	0	0	0
T4	105880	0	0	0
T9	0	1	0	0
T17	3591	1	0	0
T18	1589	0	0	0
T19	2330	0	0	0
T20	2427	0	0	0
T21	1109	1	0	0
T22	4839	0	0	0
T23	2032	0	0	0
T26	23455	0	0	0
T40	0	3	0	0
T41	0	2	0	0
T133	0	2	0	0
T150	0	4	0	0
T157	0	4	0	0
T158	0	4	0	0
T159	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476730956	128	0	0
T2	250535	0	0	0
T4	105880	0	0	0
T17	3591	1	0	0
T18	1589	0	0	0
T19	2330	0	0	0
T20	2427	0	0	0
T21	1109	1	0	0
T22	4839	0	0	0
T23	2032	0	0	0
T26	23455	0	0	0
T40	0	3	0	0
T41	0	2	0	0
T133	0	2	0	0
T150	0	4	0	0
T157	0	4	0	0
T158	0	4	0	0
T159	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T21
1	0	Unreachable
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	476730956	129	0	0
CgEnOn_A	476730956	128	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476730956	129	0	0
T2	250535	0	0	0
T4	105880	0	0	0
T9	0	1	0	0
T17	3591	1	0	0
T18	1589	0	0	0
T19	2330	0	0	0
T20	2427	0	0	0
T21	1109	1	0	0
T22	4839	0	0	0
T23	2032	0	0	0
T26	23455	0	0	0
T40	0	3	0	0
T41	0	2	0	0
T133	0	2	0	0
T150	0	4	0	0
T157	0	4	0	0
T158	0	4	0	0
T159	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476730956	128	0	0
T2	250535	0	0	0
T4	105880	0	0	0
T17	3591	1	0	0
T18	1589	0	0	0
T19	2330	0	0	0
T20	2427	0	0	0
T21	1109	1	0	0
T22	4839	0	0	0
T23	2032	0	0	0
T26	23455	0	0	0
T40	0	3	0	0
T41	0	2	0	0
T133	0	2	0	0
T150	0	4	0	0
T157	0	4	0	0
T158	0	4	0	0
T159	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T21,T2
1	0	Unreachable
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	228857014	131	0	0
CgEnOn_A	228857014	129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228857014	131	0	0
T2	120258	0	0	0
T4	50823	0	0	0
T7	1841	0	0	0
T21	532	1	0	0
T22	2323	0	0	0
T23	974	0	0	0
T26	11259	0	0	0
T27	1565	0	0	0
T28	1812	0	0	0
T29	990	0	0	0
T40	0	2	0	0
T41	0	4	0	0
T133	0	2	0	0
T150	0	4	0	0
T157	0	4	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	1	0	0
T161	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228857014	129	0	0
T2	120258	0	0	0
T4	50823	0	0	0
T7	1841	0	0	0
T21	532	1	0	0
T22	2323	0	0	0
T23	974	0	0	0
T26	11259	0	0	0
T27	1565	0	0	0
T28	1812	0	0	0
T29	990	0	0	0
T40	0	2	0	0
T41	0	4	0	0
T133	0	2	0	0
T150	0	4	0	0
T157	0	4	0	0
T158	0	6	0	0
T159	0	3	0	0
T160	0	1	0	0
T161	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T40,T41
1	0	Covered	T6,T5,T1
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	111442734	7353	0	0
CgEnOn_A	111442734	5106	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111442734	7353	0	0
T1	22074	1	0	0
T5	4793	1	0	0
T6	607	1	0	0
T16	2756	51	0	0
T17	871	2	0	0
T18	358	1	0	0
T19	532	1	0	0
T20	608	1	0	0
T21	262	1	0	0
T22	1152	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111442734	5106	0	0
T2	577261	50	0	0
T3	0	13	0	0
T4	12566	0	0	0
T9	0	105	0	0
T10	0	16	0	0
T17	871	1	0	0
T18	358	0	0	0
T19	532	0	0	0
T20	608	0	0	0
T21	262	0	0	0
T22	1152	1	0	0
T23	541	0	0	0
T26	5623	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T59	0	16	0	0
T162	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T40,T41
1	0	Covered	T6,T5,T1
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	222886692	7363	0	0
CgEnOn_A	222886692	5116	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222886692	7363	0	0
T1	44148	1	0	0
T5	9587	1	0	0
T6	1214	1	0	0
T16	5509	51	0	0
T17	1742	2	0	0
T18	716	1	0	0
T19	1065	1	0	0
T20	1219	1	0	0
T21	525	1	0	0
T22	2304	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222886692	5116	0	0
T2	115452	49	0	0
T3	0	13	0	0
T4	25133	0	0	0
T9	0	102	0	0
T10	0	20	0	0
T17	1742	1	0	0
T18	716	0	0	0
T19	1065	0	0	0
T20	1219	0	0	0
T21	525	0	0	0
T22	2304	1	0	0
T23	1085	0	0	0
T26	11246	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T59	0	18	0	0
T162	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T40,T41
1	0	Covered	T6,T5,T1
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	447206114	7386	0	0
CgEnOn_A	447206114	5132	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447206114	7386	0	0
T1	88362	1	0	0
T5	19252	1	0	0
T6	2494	1	0	0
T16	15960	51	0	0
T17	3523	2	0	0
T18	1524	1	0	0
T19	2237	1	0	0
T20	2330	1	0	0
T21	1074	1	0	0
T22	4646	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447206114	5132	0	0
T2	231811	50	0	0
T3	0	12	0	0
T4	101642	0	0	0
T9	0	102	0	0
T10	0	20	0	0
T17	3523	1	0	0
T18	1524	0	0	0
T19	2237	0	0	0
T20	2330	0	0	0
T21	1074	0	0	0
T22	4646	1	0	0
T23	1950	0	0	0
T26	22516	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T59	0	17	0	0
T162	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T40,T41
1	0	Covered	T6,T5,T1
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	228857014	7424	0	0
CgEnOn_A	228857014	5170	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228857014	7424	0	0
T1	44183	1	0	0
T5	18266	1	0	0
T6	1247	1	0	0
T16	7980	51	0	0
T17	1787	1	0	0
T18	762	1	0	0
T19	1118	1	0	0
T20	1166	1	0	0
T21	532	2	0	0
T22	2323	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228857014	5170	0	0
T2	120258	50	0	0
T3	0	13	0	0
T4	50823	0	0	0
T7	1841	0	0	0
T9	0	101	0	0
T10	0	20	0	0
T21	532	1	0	0
T22	2323	1	0	0
T23	974	0	0	0
T26	11259	0	0	0
T27	1565	0	0	0
T28	1812	0	0	0
T29	990	0	0	0
T40	0	2	0	0
T41	0	4	0	0
T59	0	16	0	0
T162	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T21
1	0	Covered	T6,T22,T2
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	476730956	3984	0	0
CgEnOn_A	476730956	3983	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476730956	3984	0	0
T1	92048	0	0	0
T2	0	23	0	0
T5	38054	0	0	0
T6	2599	5	0	0
T16	16625	0	0	0
T17	3591	1	0	0
T18	1589	0	0	0
T19	2330	0	0	0
T20	2427	0	0	0
T21	1109	1	0	0
T22	4839	1	0	0
T28	0	9	0	0
T30	0	9	0	0
T31	0	4	0	0
T32	0	7	0	0
T99	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476730956	3983	0	0
T1	92048	0	0	0
T2	0	23	0	0
T5	38054	0	0	0
T6	2599	5	0	0
T16	16625	0	0	0
T17	3591	1	0	0
T18	1589	0	0	0
T19	2330	0	0	0
T20	2427	0	0	0
T21	1109	1	0	0
T22	4839	1	0	0
T28	0	9	0	0
T30	0	9	0	0
T31	0	4	0	0
T32	0	7	0	0
T99	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T21
1	0	Covered	T6,T18,T22
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	476730956	3965	0	0
CgEnOn_A	476730956	3964	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476730956	3965	0	0
T1	92048	0	0	0
T2	0	25	0	0
T5	38054	0	0	0
T6	2599	7	0	0
T16	16625	0	0	0
T17	3591	1	0	0
T18	1589	1	0	0
T19	2330	0	0	0
T20	2427	0	0	0
T21	1109	1	0	0
T22	4839	1	0	0
T28	0	10	0	0
T30	0	5	0	0
T31	0	2	0	0
T32	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476730956	3964	0	0
T1	92048	0	0	0
T2	0	25	0	0
T5	38054	0	0	0
T6	2599	7	0	0
T16	16625	0	0	0
T17	3591	1	0	0
T18	1589	1	0	0
T19	2330	0	0	0
T20	2427	0	0	0
T21	1109	1	0	0
T22	4839	1	0	0
T28	0	10	0	0
T30	0	5	0	0
T31	0	2	0	0
T32	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T21
1	0	Covered	T6,T18,T22
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	476730956	3969	0	0
CgEnOn_A	476730956	3968	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476730956	3969	0	0
T1	92048	0	0	0
T2	0	26	0	0
T5	38054	0	0	0
T6	2599	7	0	0
T16	16625	0	0	0
T17	3591	1	0	0
T18	1589	2	0	0
T19	2330	0	0	0
T20	2427	0	0	0
T21	1109	1	0	0
T22	4839	1	0	0
T28	0	9	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476730956	3968	0	0
T1	92048	0	0	0
T2	0	26	0	0
T5	38054	0	0	0
T6	2599	7	0	0
T16	16625	0	0	0
T17	3591	1	0	0
T18	1589	2	0	0
T19	2330	0	0	0
T20	2427	0	0	0
T21	1109	1	0	0
T22	4839	1	0	0
T28	0	9	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T21
1	0	Covered	T6,T18,T22
1	1	Covered	T6,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	476730956	3925	0	0
CgEnOn_A	476730956	3924	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476730956	3925	0	0
T1	92048	0	0	0
T2	0	26	0	0
T5	38054	0	0	0
T6	2599	4	0	0
T16	16625	0	0	0
T17	3591	1	0	0
T18	1589	1	0	0
T19	2330	0	0	0
T20	2427	0	0	0
T21	1109	1	0	0
T22	4839	1	0	0
T28	0	8	0	0
T30	0	9	0	0
T32	0	8	0	0
T99	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476730956	3924	0	0
T1	92048	0	0	0
T2	0	26	0	0
T5	38054	0	0	0
T6	2599	4	0	0
T16	16625	0	0	0
T17	3591	1	0	0
T18	1589	1	0	0
T19	2330	0	0	0
T20	2427	0	0	0
T21	1109	1	0	0
T22	4839	1	0	0
T28	0	8	0	0
T30	0	9	0	0
T32	0	8	0	0
T99	0	9	0	0