Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	617512	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3558808

1

T1

1137

T5

18

T4

165

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1027625	1			T1	471		T5	17		T4	15
values[0x0]	1445499	1			T1	974		T5	14		T4	155
values[0x1]	1703196	1			T1	961		T5	21		T4	161

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	339891	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3836429

1

T1

1495

T5

23

T4

216

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15041	1			T1	6		T5	1		T3	459
valid_sources[0x01]	17497	1			T1	11		T31	1		T3	145
valid_sources[0x02]	17152	1			T1	15		T5	1		T4	1
valid_sources[0x03]	17338	1			T1	12		T4	1		T31	1
valid_sources[0x04]	16012	1			T1	13		T5	1		T4	1
valid_sources[0x05]	16011	1			T1	13		T4	2		T38	2
valid_sources[0x06]	15666	1			T1	13		T4	1		T31	1
valid_sources[0x07]	17148	1			T1	6		T4	1		T18	1
valid_sources[0x08]	16402	1			T1	9		T5	1		T4	2
valid_sources[0x09]	16009	1			T1	5		T5	1		T4	2
valid_sources[0x0a]	15911	1			T1	12		T4	5		T51	2
valid_sources[0x0b]	16261	1			T1	9		T31	1		T3	206
valid_sources[0x0c]	15485	1			T1	10		T17	1		T3	1
valid_sources[0x0d]	15242	1			T1	10		T31	1		T3	140
valid_sources[0x0e]	16574	1			T1	13		T4	2		T51	4
valid_sources[0x0f]	16512	1			T1	11		T5	2		T38	1
valid_sources[0x10]	15680	1			T1	9		T4	4		T51	1
valid_sources[0x11]	15570	1			T1	13		T5	1		T4	2
valid_sources[0x12]	15379	1			T1	9		T4	1		T38	1
valid_sources[0x13]	15106	1			T1	17		T31	1		T3	326
valid_sources[0x14]	16042	1			T1	11		T5	1		T4	2
valid_sources[0x15]	17661	1			T1	7		T18	1		T51	2
valid_sources[0x16]	15996	1			T1	1		T18	2		T3	255
valid_sources[0x17]	15333	1			T1	6		T4	1		T3	142
valid_sources[0x18]	16846	1			T1	3		T4	1		T31	1
valid_sources[0x19]	16075	1			T1	6		T3	143		T61	5
valid_sources[0x1a]	16451	1			T1	11		T4	2		T3	58
valid_sources[0x1b]	16246	1			T1	9		T4	1		T3	300
valid_sources[0x1c]	16298	1			T1	12		T4	2		T31	2
valid_sources[0x1d]	17079	1			T1	12		T4	4		T17	1
valid_sources[0x1e]	17071	1			T1	10		T4	1		T31	1
valid_sources[0x1f]	15134	1			T1	8		T31	1		T3	231
valid_sources[0x20]	15744	1			T1	6		T4	2		T18	2
valid_sources[0x21]	16968	1			T1	13		T4	1		T31	1
valid_sources[0x22]	15891	1			T1	11		T38	1		T31	1
valid_sources[0x23]	18236	1			T1	10		T4	1		T17	1
valid_sources[0x24]	15553	1			T1	8		T31	1		T104	3
valid_sources[0x25]	16260	1			T1	8		T5	1		T4	2
valid_sources[0x26]	16952	1			T1	17		T4	2		T3	8
valid_sources[0x27]	16730	1			T1	10		T4	4		T3	769
valid_sources[0x28]	15804	1			T1	14		T4	1		T3	2
valid_sources[0x29]	15825	1			T1	11		T5	1		T4	6
valid_sources[0x2a]	16606	1			T1	11		T18	1		T3	297
valid_sources[0x2b]	16589	1			T1	8		T4	2		T19	49
valid_sources[0x2c]	16931	1			T1	3		T4	3		T31	1
valid_sources[0x2d]	16839	1			T1	18		T3	567		T9	309
valid_sources[0x2e]	16234	1			T1	10		T3	65		T9	331
valid_sources[0x2f]	16758	1			T1	12		T3	367		T9	222
valid_sources[0x30]	16012	1			T1	12		T4	2		T17	1
valid_sources[0x31]	16294	1			T1	12		T9	335		T10	5
valid_sources[0x32]	16083	1			T1	6		T4	2		T104	1
valid_sources[0x33]	16080	1			T1	11		T4	1		T18	2
valid_sources[0x34]	16306	1			T1	10		T51	2		T9	315
valid_sources[0x35]	16410	1			T1	11		T4	2		T51	5
valid_sources[0x36]	16278	1			T1	10		T5	1		T17	1
valid_sources[0x37]	17602	1			T1	6		T3	837		T9	286
valid_sources[0x38]	16491	1			T1	12		T17	1		T38	1
valid_sources[0x39]	16334	1			T1	11		T38	1		T3	629
valid_sources[0x3a]	16000	1			T1	8		T31	1		T3	292
valid_sources[0x3b]	15915	1			T1	6		T18	2		T38	1
valid_sources[0x3c]	14996	1			T1	11		T9	368		T10	5
valid_sources[0x3d]	15967	1			T1	16		T4	1		T31	1
valid_sources[0x3e]	15876	1			T1	6		T4	2		T17	1
valid_sources[0x3f]	16774	1			T1	10		T17	1		T18	1
valid_sources[0x40]	15855	1			T1	5		T3	164		T9	318
valid_sources[0x41]	17146	1			T1	1		T5	1		T18	1
valid_sources[0x42]	16423	1			T1	12		T4	1		T31	2
valid_sources[0x43]	15499	1			T1	17		T4	7		T3	1
valid_sources[0x44]	15809	1			T1	10		T4	2		T31	1
valid_sources[0x45]	15895	1			T1	8		T38	1		T31	2
valid_sources[0x46]	16617	1			T1	9		T4	2		T3	738
valid_sources[0x47]	16786	1			T1	14		T31	1		T3	599
valid_sources[0x48]	15898	1			T1	17		T4	3		T18	1
valid_sources[0x49]	17223	1			T1	12		T4	3		T31	1
valid_sources[0x4a]	16357	1			T1	8		T51	2		T3	364
valid_sources[0x4b]	16967	1			T1	12		T5	1		T17	1
valid_sources[0x4c]	18435	1			T1	6		T5	1		T3	478
valid_sources[0x4d]	15537	1			T1	7		T31	1		T3	126
valid_sources[0x4e]	15253	1			T1	9		T18	3		T3	138
valid_sources[0x4f]	16796	1			T1	7		T4	1		T17	2
valid_sources[0x50]	16832	1			T1	14		T5	1		T4	1
valid_sources[0x51]	15649	1			T1	5		T4	1		T31	1
valid_sources[0x52]	15690	1			T1	8		T3	342		T9	340
valid_sources[0x53]	16729	1			T1	9		T5	1		T103	1
valid_sources[0x54]	15840	1			T1	8		T5	1		T4	2
valid_sources[0x55]	16349	1			T1	9		T31	1		T3	690
valid_sources[0x56]	16995	1			T1	14		T15	100		T3	204
valid_sources[0x57]	15782	1			T1	10		T4	3		T38	1
valid_sources[0x58]	16984	1			T1	7		T17	1		T3	64
valid_sources[0x59]	16835	1			T1	5		T3	544		T9	284
valid_sources[0x5a]	15572	1			T1	8		T4	4		T17	1
valid_sources[0x5b]	15798	1			T1	4		T4	1		T31	1
valid_sources[0x5c]	15518	1			T1	10		T4	1		T3	399
valid_sources[0x5d]	16026	1			T1	7		T5	1		T51	2
valid_sources[0x5e]	17535	1			T1	6		T5	1		T4	2
valid_sources[0x5f]	16074	1			T1	8		T4	1		T104	1
valid_sources[0x60]	16557	1			T1	14		T31	1		T3	97
valid_sources[0x61]	17142	1			T1	9		T17	1		T51	1
valid_sources[0x62]	16306	1			T1	2		T4	3		T17	2
valid_sources[0x63]	16292	1			T1	7		T3	191		T9	458
valid_sources[0x64]	16424	1			T1	12		T4	1		T18	1
valid_sources[0x65]	16516	1			T1	7		T4	1		T18	1
valid_sources[0x66]	15784	1			T1	7		T4	3		T104	1
valid_sources[0x67]	17097	1			T1	8		T5	1		T18	1
valid_sources[0x68]	16251	1			T1	8		T103	2		T3	501
valid_sources[0x69]	16027	1			T1	3		T4	4		T18	4
valid_sources[0x6a]	17669	1			T1	10		T4	5		T38	1
valid_sources[0x6b]	16077	1			T1	7		T31	1		T3	150
valid_sources[0x6c]	16356	1			T1	10		T4	3		T38	1
valid_sources[0x6d]	15303	1			T1	5		T4	1		T3	395
valid_sources[0x6e]	15023	1			T1	4		T4	2		T31	1
valid_sources[0x6f]	16559	1			T1	11		T4	1		T51	4
valid_sources[0x70]	15975	1			T1	10		T5	1		T38	1
valid_sources[0x71]	16193	1			T1	9		T9	363		T63	2
valid_sources[0x72]	18170	1			T1	12		T51	1		T3	750
valid_sources[0x73]	16121	1			T1	4		T4	2		T3	335
valid_sources[0x74]	17458	1			T1	5		T31	1		T3	445
valid_sources[0x75]	16309	1			T1	12		T4	2		T31	1
valid_sources[0x76]	15897	1			T1	9		T4	3		T31	1
valid_sources[0x77]	15448	1			T1	10		T5	1		T18	1
valid_sources[0x78]	16211	1			T1	9		T4	1		T3	97
valid_sources[0x79]	15165	1			T1	13		T4	4		T17	1
valid_sources[0x7a]	17716	1			T1	9		T4	2		T38	1
valid_sources[0x7b]	16462	1			T1	8		T18	1		T3	118
valid_sources[0x7c]	16130	1			T1	9		T38	1		T3	6
valid_sources[0x7d]	16514	1			T1	10		T4	1		T18	1
valid_sources[0x7e]	15962	1			T1	9		T5	2		T4	1
valid_sources[0x7f]	15437	1			T1	6		T38	1		T3	70
valid_sources[0x80]	15299	1			T1	13		T4	10		T18	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

898042

1

T1

221

T5

9

T4

5

values[0x0]

all_enables

biggest_size

1352467

1

T1

596

T5

6

T4

96

values[0x1]

all_enables

biggest_size

1308299

1

T1

320

T5

3

T4

64