Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T18
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T18
1	0	Covered	T32,T35,T33
1	1	Covered	T1,T5,T4

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1050043983	13522	0	0
GateOpen_A	1050043983	20398	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050043983	13522	0	0
T1	2014386	4	0	0
T2	0	77	0	0
T3	0	112	0	0
T4	324318	0	0	0
T5	5382	0	0	0
T9	0	94	0	0
T15	61506	0	0	0
T16	7727	0	0	0
T17	4579	0	0	0
T18	9750	4	0	0
T19	4538	0	0	0
T20	10932	0	0	0
T21	3012	0	0	0
T32	0	13	0	0
T61	0	3	0	0
T63	0	14	0	0
T161	0	15	0	0
T162	0	16	0	0
T163	0	12	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050043983	20398	0	0
T1	2014386	16	0	0
T4	324318	0	0	0
T5	5382	0	0	0
T15	61506	404	0	0
T16	7727	0	0	0
T17	4579	4	0	0
T18	9750	4	0	0
T19	4538	4	0	0
T20	10932	4	0	0
T21	3012	4	0	0
T31	0	4	0	0
T32	0	17	0	0
T103	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T18
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T18
1	0	Covered	T32,T33,T34
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	115851949	3203	0	0
GateOpen_A	115851949	4922	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115851949	3203	0	0
T1	220215	1	0	0
T2	0	19	0	0
T3	0	27	0	0
T4	35062	0	0	0
T5	632	0	0	0
T9	0	22	0	0
T15	5439	0	0	0
T16	839	0	0	0
T17	505	0	0	0
T18	1077	1	0	0
T19	526	0	0	0
T20	1193	0	0	0
T21	330	0	0	0
T32	0	3	0	0
T63	0	4	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	12	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115851949	4922	0	0
T1	220215	4	0	0
T4	35062	0	0	0
T5	632	0	0	0
T15	5439	101	0	0
T16	839	0	0	0
T17	505	1	0	0
T18	1077	1	0	0
T19	526	1	0	0
T20	1193	1	0	0
T21	330	1	0	0
T31	0	1	0	0
T32	0	4	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T18
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T18
1	0	Covered	T32,T33,T34
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	231704779	3449	0	0
GateOpen_A	231704779	5168	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231704779	3449	0	0
T1	440432	1	0	0
T2	0	20	0	0
T3	0	29	0	0
T4	70124	0	0	0
T5	1270	0	0	0
T9	0	26	0	0
T15	10887	0	0	0
T16	1677	0	0	0
T17	1010	0	0	0
T18	2154	1	0	0
T19	1052	0	0	0
T20	2385	0	0	0
T21	660	0	0	0
T32	0	3	0	0
T61	0	1	0	0
T63	0	3	0	0
T161	0	4	0	0
T162	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231704779	5168	0	0
T1	440432	4	0	0
T4	70124	0	0	0
T5	1270	0	0	0
T15	10887	101	0	0
T16	1677	0	0	0
T17	1010	1	0	0
T18	2154	1	0	0
T19	1052	1	0	0
T20	2385	1	0	0
T21	660	1	0	0
T31	0	1	0	0
T32	0	4	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T18
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T18
1	0	Covered	T32,T33,T34
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	465028432	3432	0	0
GateOpen_A	465028432	5151	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465028432	3432	0	0
T1	881358	1	0	0
T2	0	19	0	0
T3	0	30	0	0
T4	140326	0	0	0
T5	2320	0	0	0
T9	0	23	0	0
T15	30119	0	0	0
T16	3474	0	0	0
T17	2043	0	0	0
T18	4346	1	0	0
T19	1973	0	0	0
T20	4903	0	0	0
T21	1348	0	0	0
T32	0	3	0	0
T61	0	1	0	0
T63	0	3	0	0
T161	0	4	0	0
T162	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465028432	5151	0	0
T1	881358	4	0	0
T4	140326	0	0	0
T5	2320	0	0	0
T15	30119	101	0	0
T16	3474	0	0	0
T17	2043	1	0	0
T18	4346	1	0	0
T19	1973	1	0	0
T20	4903	1	0	0
T21	1348	1	0	0
T31	0	1	0	0
T32	0	4	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T18
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T18
1	0	Covered	T32,T35,T33
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	237458823	3438	0	0
GateOpen_A	237458823	5157	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237458823	3438	0	0
T1	472381	1	0	0
T2	0	19	0	0
T3	0	26	0	0
T4	78806	0	0	0
T5	1160	0	0	0
T9	0	23	0	0
T15	15061	0	0	0
T16	1737	0	0	0
T17	1021	0	0	0
T18	2173	1	0	0
T19	987	0	0	0
T20	2451	0	0	0
T21	674	0	0	0
T32	0	4	0	0
T61	0	1	0	0
T63	0	4	0	0
T161	0	4	0	0
T162	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237458823	5157	0	0
T1	472381	4	0	0
T4	78806	0	0	0
T5	1160	0	0	0
T15	15061	101	0	0
T16	1737	0	0	0
T17	1021	1	0	0
T18	2173	1	0	0
T19	987	1	0	0
T20	2451	1	0	0
T21	674	1	0	0
T31	0	1	0	0
T32	0	5	0	0
T103	0	1	0	0