Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	765143590	75544	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	765143590	75544	0	0
T1	1892590	821	0	0
T2	0	755	0	0
T3	0	1266	0	0
T4	910885	0	0	0
T5	11725	0	0	0
T8	0	61	0	0
T9	0	608	0	0
T10	0	730	0	0
T11	0	80	0	0
T12	0	356	0	0
T13	0	273	0	0
T14	0	76	0	0
T15	155305	0	0	0
T16	9040	0	0	0
T17	10425	0	0	0
T18	5205	0	0	0
T19	9760	0	0	0
T20	4590	0	0	0
T21	6810	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153028718	11360	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	11360	0	0
T1	378518	125	0	0
T2	0	122	0	0
T3	0	161	0	0
T4	182177	0	0	0
T5	2345	0	0	0
T8	0	12	0	0
T9	0	106	0	0
T10	0	94	0	0
T11	0	15	0	0
T12	0	47	0	0
T13	0	44	0	0
T14	0	14	0	0
T15	31061	0	0	0
T16	1808	0	0	0
T17	2085	0	0	0
T18	1041	0	0	0
T19	1952	0	0	0
T20	918	0	0	0
T21	1362	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153028718	10986	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	10986	0	0
T1	378518	123	0	0
T2	0	117	0	0
T3	0	181	0	0
T4	182177	0	0	0
T5	2345	0	0	0
T8	0	12	0	0
T9	0	106	0	0
T10	0	106	0	0
T11	0	15	0	0
T12	0	47	0	0
T13	0	43	0	0
T14	0	14	0	0
T15	31061	0	0	0
T16	1808	0	0	0
T17	2085	0	0	0
T18	1041	0	0	0
T19	1952	0	0	0
T20	918	0	0	0
T21	1362	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153028718	15169	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	15169	0	0
T1	378518	163	0	0
T2	0	152	0	0
T3	0	252	0	0
T4	182177	0	0	0
T5	2345	0	0	0
T8	0	12	0	0
T9	0	122	0	0
T10	0	145	0	0
T11	0	15	0	0
T12	0	73	0	0
T13	0	53	0	0
T14	0	14	0	0
T15	31061	0	0	0
T16	1808	0	0	0
T17	2085	0	0	0
T18	1041	0	0	0
T19	1952	0	0	0
T20	918	0	0	0
T21	1362	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153028718	15139	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	15139	0	0
T1	378518	165	0	0
T2	0	153	0	0
T3	0	250	0	0
T4	182177	0	0	0
T5	2345	0	0	0
T8	0	12	0	0
T9	0	121	0	0
T10	0	143	0	0
T11	0	15	0	0
T12	0	74	0	0
T13	0	53	0	0
T14	0	15	0	0
T15	31061	0	0	0
T16	1808	0	0	0
T17	2085	0	0	0
T18	1041	0	0	0
T19	1952	0	0	0
T20	918	0	0	0
T21	1362	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	153028718	22890	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	22890	0	0
T1	378518	245	0	0
T2	0	211	0	0
T3	0	422	0	0
T4	182177	0	0	0
T5	2345	0	0	0
T8	0	13	0	0
T9	0	153	0	0
T10	0	242	0	0
T11	0	20	0	0
T12	0	115	0	0
T13	0	80	0	0
T14	0	19	0	0
T15	31061	0	0	0
T16	1808	0	0	0
T17	2085	0	0	0
T18	1041	0	0	0
T19	1952	0	0	0
T20	918	0	0	0
T21	1362	0	0	0