Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22512 |
22512 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T15 |
28 |
28 |
0 |
0 |
T16 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
T19 |
28 |
28 |
0 |
0 |
T20 |
28 |
28 |
0 |
0 |
T21 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
17051983 |
17029506 |
0 |
0 |
T4 |
4384714 |
4380310 |
0 |
0 |
T5 |
62284 |
58957 |
0 |
0 |
T15 |
808851 |
388367 |
0 |
0 |
T16 |
69071 |
66296 |
0 |
0 |
T17 |
54961 |
53305 |
0 |
0 |
T18 |
69401 |
68474 |
0 |
0 |
T19 |
52332 |
48374 |
0 |
0 |
T20 |
74657 |
71567 |
0 |
0 |
T21 |
36053 |
31116 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
918172308 |
903200526 |
0 |
14472 |
T1 |
2271108 |
2267688 |
0 |
18 |
T4 |
1093062 |
1091946 |
0 |
18 |
T5 |
14070 |
13236 |
0 |
18 |
T15 |
186366 |
80700 |
0 |
18 |
T16 |
10848 |
10368 |
0 |
18 |
T17 |
12510 |
12090 |
0 |
18 |
T18 |
6246 |
6138 |
0 |
18 |
T19 |
11712 |
10734 |
0 |
18 |
T20 |
5508 |
5238 |
0 |
18 |
T21 |
8172 |
6924 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16884 |
T1 |
5574833 |
5566403 |
0 |
21 |
T4 |
1113388 |
1112093 |
0 |
21 |
T5 |
16678 |
15690 |
0 |
21 |
T15 |
217740 |
94084 |
0 |
21 |
T16 |
21561 |
20617 |
0 |
21 |
T17 |
14724 |
14226 |
0 |
21 |
T18 |
24531 |
24137 |
0 |
21 |
T19 |
14097 |
12918 |
0 |
21 |
T20 |
27171 |
25871 |
0 |
21 |
T21 |
9684 |
8202 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
197730 |
0 |
0 |
T1 |
5574833 |
500 |
0 |
0 |
T2 |
0 |
33 |
0 |
0 |
T3 |
0 |
600 |
0 |
0 |
T4 |
1113388 |
4 |
0 |
0 |
T5 |
16678 |
192 |
0 |
0 |
T15 |
217740 |
12 |
0 |
0 |
T16 |
21561 |
12 |
0 |
0 |
T17 |
14724 |
118 |
0 |
0 |
T18 |
24531 |
12 |
0 |
0 |
T19 |
14097 |
123 |
0 |
0 |
T20 |
27171 |
13 |
0 |
0 |
T21 |
9684 |
17 |
0 |
0 |
T38 |
0 |
147 |
0 |
0 |
T59 |
0 |
7 |
0 |
0 |
T103 |
0 |
41 |
0 |
0 |
T104 |
0 |
84 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
9206042 |
9195064 |
0 |
0 |
T4 |
2178264 |
2176232 |
0 |
0 |
T5 |
31536 |
29992 |
0 |
0 |
T15 |
404745 |
209548 |
0 |
0 |
T16 |
36662 |
35272 |
0 |
0 |
T17 |
27727 |
26950 |
0 |
0 |
T18 |
38624 |
38160 |
0 |
0 |
T19 |
26523 |
24683 |
0 |
0 |
T20 |
41978 |
40419 |
0 |
0 |
T21 |
18197 |
15951 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T17 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T17 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T17 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T17 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T17 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
465028000 |
460615938 |
0 |
0 |
T1 |
881357 |
879974 |
0 |
0 |
T4 |
140326 |
140150 |
0 |
0 |
T5 |
2320 |
2185 |
0 |
0 |
T15 |
30118 |
13295 |
0 |
0 |
T16 |
3473 |
3324 |
0 |
0 |
T17 |
2042 |
1975 |
0 |
0 |
T18 |
4345 |
4278 |
0 |
0 |
T19 |
1973 |
1811 |
0 |
0 |
T20 |
4903 |
4672 |
0 |
0 |
T21 |
1348 |
1145 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
465028000 |
460608834 |
0 |
2412 |
T1 |
881357 |
879947 |
0 |
3 |
T4 |
140326 |
140147 |
0 |
3 |
T5 |
2320 |
2182 |
0 |
3 |
T15 |
30118 |
12992 |
0 |
3 |
T16 |
3473 |
3321 |
0 |
3 |
T17 |
2042 |
1972 |
0 |
3 |
T18 |
4345 |
4275 |
0 |
3 |
T19 |
1973 |
1808 |
0 |
3 |
T20 |
4903 |
4669 |
0 |
3 |
T21 |
1348 |
1142 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
465028000 |
27469 |
0 |
0 |
T1 |
881357 |
16 |
0 |
0 |
T2 |
0 |
12 |
0 |
0 |
T3 |
0 |
251 |
0 |
0 |
T4 |
140326 |
0 |
0 |
0 |
T5 |
2320 |
59 |
0 |
0 |
T15 |
30118 |
0 |
0 |
0 |
T16 |
3473 |
0 |
0 |
0 |
T17 |
2042 |
27 |
0 |
0 |
T18 |
4345 |
0 |
0 |
0 |
T19 |
1973 |
33 |
0 |
0 |
T20 |
4903 |
0 |
0 |
0 |
T21 |
1348 |
4 |
0 |
0 |
T38 |
0 |
84 |
0 |
0 |
T103 |
0 |
15 |
0 |
0 |
T104 |
0 |
37 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T17 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T17 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T17 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T17 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T17 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150533421 |
0 |
2412 |
T1 |
378518 |
377948 |
0 |
3 |
T4 |
182177 |
181991 |
0 |
3 |
T5 |
2345 |
2206 |
0 |
3 |
T15 |
31061 |
13450 |
0 |
3 |
T16 |
1808 |
1728 |
0 |
3 |
T17 |
2085 |
2015 |
0 |
3 |
T18 |
1041 |
1023 |
0 |
3 |
T19 |
1952 |
1789 |
0 |
3 |
T20 |
918 |
873 |
0 |
3 |
T21 |
1362 |
1154 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
17011 |
0 |
0 |
T1 |
378518 |
9 |
0 |
0 |
T2 |
0 |
7 |
0 |
0 |
T3 |
0 |
148 |
0 |
0 |
T4 |
182177 |
0 |
0 |
0 |
T5 |
2345 |
36 |
0 |
0 |
T15 |
31061 |
0 |
0 |
0 |
T16 |
1808 |
0 |
0 |
0 |
T17 |
2085 |
14 |
0 |
0 |
T18 |
1041 |
0 |
0 |
0 |
T19 |
1952 |
0 |
0 |
0 |
T20 |
918 |
0 |
0 |
0 |
T21 |
1362 |
3 |
0 |
0 |
T38 |
0 |
31 |
0 |
0 |
T59 |
0 |
6 |
0 |
0 |
T103 |
0 |
15 |
0 |
0 |
T104 |
0 |
19 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T17 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T17 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T17 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T17 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T17 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150533421 |
0 |
2412 |
T1 |
378518 |
377948 |
0 |
3 |
T4 |
182177 |
181991 |
0 |
3 |
T5 |
2345 |
2206 |
0 |
3 |
T15 |
31061 |
13450 |
0 |
3 |
T16 |
1808 |
1728 |
0 |
3 |
T17 |
2085 |
2015 |
0 |
3 |
T18 |
1041 |
1023 |
0 |
3 |
T19 |
1952 |
1789 |
0 |
3 |
T20 |
918 |
873 |
0 |
3 |
T21 |
1362 |
1154 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
19341 |
0 |
0 |
T1 |
378518 |
13 |
0 |
0 |
T2 |
0 |
14 |
0 |
0 |
T3 |
0 |
201 |
0 |
0 |
T4 |
182177 |
0 |
0 |
0 |
T5 |
2345 |
47 |
0 |
0 |
T15 |
31061 |
0 |
0 |
0 |
T16 |
1808 |
0 |
0 |
0 |
T17 |
2085 |
19 |
0 |
0 |
T18 |
1041 |
0 |
0 |
0 |
T19 |
1952 |
32 |
0 |
0 |
T20 |
918 |
0 |
0 |
0 |
T21 |
1362 |
0 |
0 |
0 |
T38 |
0 |
32 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
T103 |
0 |
11 |
0 |
0 |
T104 |
0 |
28 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
492623844 |
0 |
0 |
T1 |
984110 |
983312 |
0 |
0 |
T4 |
152177 |
152094 |
0 |
0 |
T5 |
2417 |
2348 |
0 |
0 |
T15 |
31375 |
22631 |
0 |
0 |
T16 |
3618 |
3492 |
0 |
0 |
T17 |
2128 |
2087 |
0 |
0 |
T18 |
4526 |
4486 |
0 |
0 |
T19 |
2055 |
1971 |
0 |
0 |
T20 |
5108 |
4967 |
0 |
0 |
T21 |
1403 |
1334 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
492623844 |
0 |
0 |
T1 |
984110 |
983312 |
0 |
0 |
T4 |
152177 |
152094 |
0 |
0 |
T5 |
2417 |
2348 |
0 |
0 |
T15 |
31375 |
22631 |
0 |
0 |
T16 |
3618 |
3492 |
0 |
0 |
T17 |
2128 |
2087 |
0 |
0 |
T18 |
4526 |
4486 |
0 |
0 |
T19 |
2055 |
1971 |
0 |
0 |
T20 |
5108 |
4967 |
0 |
0 |
T21 |
1403 |
1334 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
465028000 |
462830473 |
0 |
0 |
T1 |
881357 |
880590 |
0 |
0 |
T4 |
140326 |
140246 |
0 |
0 |
T5 |
2320 |
2254 |
0 |
0 |
T15 |
30118 |
21725 |
0 |
0 |
T16 |
3473 |
3352 |
0 |
0 |
T17 |
2042 |
2003 |
0 |
0 |
T18 |
4345 |
4306 |
0 |
0 |
T19 |
1973 |
1893 |
0 |
0 |
T20 |
4903 |
4768 |
0 |
0 |
T21 |
1348 |
1282 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
465028000 |
462830473 |
0 |
0 |
T1 |
881357 |
880590 |
0 |
0 |
T4 |
140326 |
140246 |
0 |
0 |
T5 |
2320 |
2254 |
0 |
0 |
T15 |
30118 |
21725 |
0 |
0 |
T16 |
3473 |
3352 |
0 |
0 |
T17 |
2042 |
2003 |
0 |
0 |
T18 |
4345 |
4306 |
0 |
0 |
T19 |
1973 |
1893 |
0 |
0 |
T20 |
4903 |
4768 |
0 |
0 |
T21 |
1348 |
1282 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
231704379 |
231704379 |
0 |
0 |
T1 |
440432 |
440432 |
0 |
0 |
T4 |
70123 |
70123 |
0 |
0 |
T5 |
1269 |
1269 |
0 |
0 |
T15 |
10887 |
10887 |
0 |
0 |
T16 |
1676 |
1676 |
0 |
0 |
T17 |
1010 |
1010 |
0 |
0 |
T18 |
2153 |
2153 |
0 |
0 |
T19 |
1052 |
1052 |
0 |
0 |
T20 |
2384 |
2384 |
0 |
0 |
T21 |
659 |
659 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
231704379 |
231704379 |
0 |
0 |
T1 |
440432 |
440432 |
0 |
0 |
T4 |
70123 |
70123 |
0 |
0 |
T5 |
1269 |
1269 |
0 |
0 |
T15 |
10887 |
10887 |
0 |
0 |
T16 |
1676 |
1676 |
0 |
0 |
T17 |
1010 |
1010 |
0 |
0 |
T18 |
2153 |
2153 |
0 |
0 |
T19 |
1052 |
1052 |
0 |
0 |
T20 |
2384 |
2384 |
0 |
0 |
T21 |
659 |
659 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
115851573 |
115851573 |
0 |
0 |
T1 |
220215 |
220215 |
0 |
0 |
T4 |
35062 |
35062 |
0 |
0 |
T5 |
632 |
632 |
0 |
0 |
T15 |
5439 |
5439 |
0 |
0 |
T16 |
838 |
838 |
0 |
0 |
T17 |
504 |
504 |
0 |
0 |
T18 |
1077 |
1077 |
0 |
0 |
T19 |
525 |
525 |
0 |
0 |
T20 |
1192 |
1192 |
0 |
0 |
T21 |
329 |
329 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
115851573 |
115851573 |
0 |
0 |
T1 |
220215 |
220215 |
0 |
0 |
T4 |
35062 |
35062 |
0 |
0 |
T5 |
632 |
632 |
0 |
0 |
T15 |
5439 |
5439 |
0 |
0 |
T16 |
838 |
838 |
0 |
0 |
T17 |
504 |
504 |
0 |
0 |
T18 |
1077 |
1077 |
0 |
0 |
T19 |
525 |
525 |
0 |
0 |
T20 |
1192 |
1192 |
0 |
0 |
T21 |
329 |
329 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
237458420 |
236351329 |
0 |
0 |
T1 |
472380 |
471997 |
0 |
0 |
T4 |
78806 |
78767 |
0 |
0 |
T5 |
1160 |
1127 |
0 |
0 |
T15 |
15060 |
10872 |
0 |
0 |
T16 |
1737 |
1676 |
0 |
0 |
T17 |
1021 |
1002 |
0 |
0 |
T18 |
2173 |
2154 |
0 |
0 |
T19 |
986 |
946 |
0 |
0 |
T20 |
2451 |
2384 |
0 |
0 |
T21 |
674 |
641 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
237458420 |
236351329 |
0 |
0 |
T1 |
472380 |
471997 |
0 |
0 |
T4 |
78806 |
78767 |
0 |
0 |
T5 |
1160 |
1127 |
0 |
0 |
T15 |
15060 |
10872 |
0 |
0 |
T16 |
1737 |
1676 |
0 |
0 |
T17 |
1021 |
1002 |
0 |
0 |
T18 |
2173 |
2154 |
0 |
0 |
T19 |
986 |
946 |
0 |
0 |
T20 |
2451 |
2384 |
0 |
0 |
T21 |
674 |
641 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150533421 |
0 |
2412 |
T1 |
378518 |
377948 |
0 |
3 |
T4 |
182177 |
181991 |
0 |
3 |
T5 |
2345 |
2206 |
0 |
3 |
T15 |
31061 |
13450 |
0 |
3 |
T16 |
1808 |
1728 |
0 |
3 |
T17 |
2085 |
2015 |
0 |
3 |
T18 |
1041 |
1023 |
0 |
3 |
T19 |
1952 |
1789 |
0 |
3 |
T20 |
918 |
873 |
0 |
3 |
T21 |
1362 |
1154 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150533421 |
0 |
2412 |
T1 |
378518 |
377948 |
0 |
3 |
T4 |
182177 |
181991 |
0 |
3 |
T5 |
2345 |
2206 |
0 |
3 |
T15 |
31061 |
13450 |
0 |
3 |
T16 |
1808 |
1728 |
0 |
3 |
T17 |
2085 |
2015 |
0 |
3 |
T18 |
1041 |
1023 |
0 |
3 |
T19 |
1952 |
1789 |
0 |
3 |
T20 |
918 |
873 |
0 |
3 |
T21 |
1362 |
1154 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150533421 |
0 |
2412 |
T1 |
378518 |
377948 |
0 |
3 |
T4 |
182177 |
181991 |
0 |
3 |
T5 |
2345 |
2206 |
0 |
3 |
T15 |
31061 |
13450 |
0 |
3 |
T16 |
1808 |
1728 |
0 |
3 |
T17 |
2085 |
2015 |
0 |
3 |
T18 |
1041 |
1023 |
0 |
3 |
T19 |
1952 |
1789 |
0 |
3 |
T20 |
918 |
873 |
0 |
3 |
T21 |
1362 |
1154 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150533421 |
0 |
2412 |
T1 |
378518 |
377948 |
0 |
3 |
T4 |
182177 |
181991 |
0 |
3 |
T5 |
2345 |
2206 |
0 |
3 |
T15 |
31061 |
13450 |
0 |
3 |
T16 |
1808 |
1728 |
0 |
3 |
T17 |
2085 |
2015 |
0 |
3 |
T18 |
1041 |
1023 |
0 |
3 |
T19 |
1952 |
1789 |
0 |
3 |
T20 |
918 |
873 |
0 |
3 |
T21 |
1362 |
1154 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150533421 |
0 |
2412 |
T1 |
378518 |
377948 |
0 |
3 |
T4 |
182177 |
181991 |
0 |
3 |
T5 |
2345 |
2206 |
0 |
3 |
T15 |
31061 |
13450 |
0 |
3 |
T16 |
1808 |
1728 |
0 |
3 |
T17 |
2085 |
2015 |
0 |
3 |
T18 |
1041 |
1023 |
0 |
3 |
T19 |
1952 |
1789 |
0 |
3 |
T20 |
918 |
873 |
0 |
3 |
T21 |
1362 |
1154 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150533421 |
0 |
2412 |
T1 |
378518 |
377948 |
0 |
3 |
T4 |
182177 |
181991 |
0 |
3 |
T5 |
2345 |
2206 |
0 |
3 |
T15 |
31061 |
13450 |
0 |
3 |
T16 |
1808 |
1728 |
0 |
3 |
T17 |
2085 |
2015 |
0 |
3 |
T18 |
1041 |
1023 |
0 |
3 |
T19 |
1952 |
1789 |
0 |
3 |
T20 |
918 |
873 |
0 |
3 |
T21 |
1362 |
1154 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153028718 |
150540682 |
0 |
0 |
T1 |
378518 |
377975 |
0 |
0 |
T4 |
182177 |
181994 |
0 |
0 |
T5 |
2345 |
2209 |
0 |
0 |
T15 |
31061 |
13765 |
0 |
0 |
T16 |
1808 |
1731 |
0 |
0 |
T17 |
2085 |
2018 |
0 |
0 |
T18 |
1041 |
1026 |
0 |
0 |
T19 |
1952 |
1792 |
0 |
0 |
T20 |
918 |
876 |
0 |
0 |
T21 |
1362 |
1157 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490294591 |
0 |
0 |
T1 |
984110 |
982667 |
0 |
0 |
T4 |
152177 |
151994 |
0 |
0 |
T5 |
2417 |
2277 |
0 |
0 |
T15 |
31375 |
13851 |
0 |
0 |
T16 |
3618 |
3463 |
0 |
0 |
T17 |
2128 |
2059 |
0 |
0 |
T18 |
4526 |
4457 |
0 |
0 |
T19 |
2055 |
1886 |
0 |
0 |
T20 |
5108 |
4867 |
0 |
0 |
T21 |
1403 |
1191 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490287464 |
0 |
2412 |
T1 |
984110 |
982640 |
0 |
3 |
T4 |
152177 |
151991 |
0 |
3 |
T5 |
2417 |
2274 |
0 |
3 |
T15 |
31375 |
13548 |
0 |
3 |
T16 |
3618 |
3460 |
0 |
3 |
T17 |
2128 |
2056 |
0 |
3 |
T18 |
4526 |
4454 |
0 |
3 |
T19 |
2055 |
1883 |
0 |
3 |
T20 |
5108 |
4864 |
0 |
3 |
T21 |
1403 |
1188 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
33457 |
0 |
0 |
T1 |
984110 |
121 |
0 |
0 |
T4 |
152177 |
1 |
0 |
0 |
T5 |
2417 |
10 |
0 |
0 |
T15 |
31375 |
3 |
0 |
0 |
T16 |
3618 |
3 |
0 |
0 |
T17 |
2128 |
13 |
0 |
0 |
T18 |
4526 |
3 |
0 |
0 |
T19 |
2055 |
13 |
0 |
0 |
T20 |
5108 |
4 |
0 |
0 |
T21 |
1403 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490294591 |
0 |
0 |
T1 |
984110 |
982667 |
0 |
0 |
T4 |
152177 |
151994 |
0 |
0 |
T5 |
2417 |
2277 |
0 |
0 |
T15 |
31375 |
13851 |
0 |
0 |
T16 |
3618 |
3463 |
0 |
0 |
T17 |
2128 |
2059 |
0 |
0 |
T18 |
4526 |
4457 |
0 |
0 |
T19 |
2055 |
1886 |
0 |
0 |
T20 |
5108 |
4867 |
0 |
0 |
T21 |
1403 |
1191 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490294591 |
0 |
0 |
T1 |
984110 |
982667 |
0 |
0 |
T4 |
152177 |
151994 |
0 |
0 |
T5 |
2417 |
2277 |
0 |
0 |
T15 |
31375 |
13851 |
0 |
0 |
T16 |
3618 |
3463 |
0 |
0 |
T17 |
2128 |
2059 |
0 |
0 |
T18 |
4526 |
4457 |
0 |
0 |
T19 |
2055 |
1886 |
0 |
0 |
T20 |
5108 |
4867 |
0 |
0 |
T21 |
1403 |
1191 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490294591 |
0 |
0 |
T1 |
984110 |
982667 |
0 |
0 |
T4 |
152177 |
151994 |
0 |
0 |
T5 |
2417 |
2277 |
0 |
0 |
T15 |
31375 |
13851 |
0 |
0 |
T16 |
3618 |
3463 |
0 |
0 |
T17 |
2128 |
2059 |
0 |
0 |
T18 |
4526 |
4457 |
0 |
0 |
T19 |
2055 |
1886 |
0 |
0 |
T20 |
5108 |
4867 |
0 |
0 |
T21 |
1403 |
1191 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490287464 |
0 |
2412 |
T1 |
984110 |
982640 |
0 |
3 |
T4 |
152177 |
151991 |
0 |
3 |
T5 |
2417 |
2274 |
0 |
3 |
T15 |
31375 |
13548 |
0 |
3 |
T16 |
3618 |
3460 |
0 |
3 |
T17 |
2128 |
2056 |
0 |
3 |
T18 |
4526 |
4454 |
0 |
3 |
T19 |
2055 |
1883 |
0 |
3 |
T20 |
5108 |
4864 |
0 |
3 |
T21 |
1403 |
1188 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
33405 |
0 |
0 |
T1 |
984110 |
99 |
0 |
0 |
T4 |
152177 |
1 |
0 |
0 |
T5 |
2417 |
19 |
0 |
0 |
T15 |
31375 |
3 |
0 |
0 |
T16 |
3618 |
3 |
0 |
0 |
T17 |
2128 |
17 |
0 |
0 |
T18 |
4526 |
3 |
0 |
0 |
T19 |
2055 |
15 |
0 |
0 |
T20 |
5108 |
1 |
0 |
0 |
T21 |
1403 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490294591 |
0 |
0 |
T1 |
984110 |
982667 |
0 |
0 |
T4 |
152177 |
151994 |
0 |
0 |
T5 |
2417 |
2277 |
0 |
0 |
T15 |
31375 |
13851 |
0 |
0 |
T16 |
3618 |
3463 |
0 |
0 |
T17 |
2128 |
2059 |
0 |
0 |
T18 |
4526 |
4457 |
0 |
0 |
T19 |
2055 |
1886 |
0 |
0 |
T20 |
5108 |
4867 |
0 |
0 |
T21 |
1403 |
1191 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490294591 |
0 |
0 |
T1 |
984110 |
982667 |
0 |
0 |
T4 |
152177 |
151994 |
0 |
0 |
T5 |
2417 |
2277 |
0 |
0 |
T15 |
31375 |
13851 |
0 |
0 |
T16 |
3618 |
3463 |
0 |
0 |
T17 |
2128 |
2059 |
0 |
0 |
T18 |
4526 |
4457 |
0 |
0 |
T19 |
2055 |
1886 |
0 |
0 |
T20 |
5108 |
4867 |
0 |
0 |
T21 |
1403 |
1191 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490294591 |
0 |
0 |
T1 |
984110 |
982667 |
0 |
0 |
T4 |
152177 |
151994 |
0 |
0 |
T5 |
2417 |
2277 |
0 |
0 |
T15 |
31375 |
13851 |
0 |
0 |
T16 |
3618 |
3463 |
0 |
0 |
T17 |
2128 |
2059 |
0 |
0 |
T18 |
4526 |
4457 |
0 |
0 |
T19 |
2055 |
1886 |
0 |
0 |
T20 |
5108 |
4867 |
0 |
0 |
T21 |
1403 |
1191 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490287464 |
0 |
2412 |
T1 |
984110 |
982640 |
0 |
3 |
T4 |
152177 |
151991 |
0 |
3 |
T5 |
2417 |
2274 |
0 |
3 |
T15 |
31375 |
13548 |
0 |
3 |
T16 |
3618 |
3460 |
0 |
3 |
T17 |
2128 |
2056 |
0 |
3 |
T18 |
4526 |
4454 |
0 |
3 |
T19 |
2055 |
1883 |
0 |
3 |
T20 |
5108 |
4864 |
0 |
3 |
T21 |
1403 |
1188 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
33678 |
0 |
0 |
T1 |
984110 |
126 |
0 |
0 |
T4 |
152177 |
1 |
0 |
0 |
T5 |
2417 |
10 |
0 |
0 |
T15 |
31375 |
3 |
0 |
0 |
T16 |
3618 |
3 |
0 |
0 |
T17 |
2128 |
15 |
0 |
0 |
T18 |
4526 |
3 |
0 |
0 |
T19 |
2055 |
17 |
0 |
0 |
T20 |
5108 |
4 |
0 |
0 |
T21 |
1403 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490294591 |
0 |
0 |
T1 |
984110 |
982667 |
0 |
0 |
T4 |
152177 |
151994 |
0 |
0 |
T5 |
2417 |
2277 |
0 |
0 |
T15 |
31375 |
13851 |
0 |
0 |
T16 |
3618 |
3463 |
0 |
0 |
T17 |
2128 |
2059 |
0 |
0 |
T18 |
4526 |
4457 |
0 |
0 |
T19 |
2055 |
1886 |
0 |
0 |
T20 |
5108 |
4867 |
0 |
0 |
T21 |
1403 |
1191 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490294591 |
0 |
0 |
T1 |
984110 |
982667 |
0 |
0 |
T4 |
152177 |
151994 |
0 |
0 |
T5 |
2417 |
2277 |
0 |
0 |
T15 |
31375 |
13851 |
0 |
0 |
T16 |
3618 |
3463 |
0 |
0 |
T17 |
2128 |
2059 |
0 |
0 |
T18 |
4526 |
4457 |
0 |
0 |
T19 |
2055 |
1886 |
0 |
0 |
T20 |
5108 |
4867 |
0 |
0 |
T21 |
1403 |
1191 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490294591 |
0 |
0 |
T1 |
984110 |
982667 |
0 |
0 |
T4 |
152177 |
151994 |
0 |
0 |
T5 |
2417 |
2277 |
0 |
0 |
T15 |
31375 |
13851 |
0 |
0 |
T16 |
3618 |
3463 |
0 |
0 |
T17 |
2128 |
2059 |
0 |
0 |
T18 |
4526 |
4457 |
0 |
0 |
T19 |
2055 |
1886 |
0 |
0 |
T20 |
5108 |
4867 |
0 |
0 |
T21 |
1403 |
1191 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490287464 |
0 |
2412 |
T1 |
984110 |
982640 |
0 |
3 |
T4 |
152177 |
151991 |
0 |
3 |
T5 |
2417 |
2274 |
0 |
3 |
T15 |
31375 |
13548 |
0 |
3 |
T16 |
3618 |
3460 |
0 |
3 |
T17 |
2128 |
2056 |
0 |
3 |
T18 |
4526 |
4454 |
0 |
3 |
T19 |
2055 |
1883 |
0 |
3 |
T20 |
5108 |
4864 |
0 |
3 |
T21 |
1403 |
1188 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
33369 |
0 |
0 |
T1 |
984110 |
116 |
0 |
0 |
T4 |
152177 |
1 |
0 |
0 |
T5 |
2417 |
11 |
0 |
0 |
T15 |
31375 |
3 |
0 |
0 |
T16 |
3618 |
3 |
0 |
0 |
T17 |
2128 |
13 |
0 |
0 |
T18 |
4526 |
3 |
0 |
0 |
T19 |
2055 |
13 |
0 |
0 |
T20 |
5108 |
4 |
0 |
0 |
T21 |
1403 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
804 |
804 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490294591 |
0 |
0 |
T1 |
984110 |
982667 |
0 |
0 |
T4 |
152177 |
151994 |
0 |
0 |
T5 |
2417 |
2277 |
0 |
0 |
T15 |
31375 |
13851 |
0 |
0 |
T16 |
3618 |
3463 |
0 |
0 |
T17 |
2128 |
2059 |
0 |
0 |
T18 |
4526 |
4457 |
0 |
0 |
T19 |
2055 |
1886 |
0 |
0 |
T20 |
5108 |
4867 |
0 |
0 |
T21 |
1403 |
1191 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
494933814 |
490294591 |
0 |
0 |
T1 |
984110 |
982667 |
0 |
0 |
T4 |
152177 |
151994 |
0 |
0 |
T5 |
2417 |
2277 |
0 |
0 |
T15 |
31375 |
13851 |
0 |
0 |
T16 |
3618 |
3463 |
0 |
0 |
T17 |
2128 |
2059 |
0 |
0 |
T18 |
4526 |
4457 |
0 |
0 |
T19 |
2055 |
1886 |
0 |
0 |
T20 |
5108 |
4867 |
0 |
0 |
T21 |
1403 |
1191 |
0 |
0 |