Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T4
0	1	Unreachable
1	0	Covered	T1,T15,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	153028718	150412611	0	0
AllClkBypReqTrue_A	153028718	125703	0	0
IoClkBypReqFalse_A	153028718	150330973	0	2412
IoClkBypReqTrue_A	153028718	202605	0	0
LcClkBypAckFalse_A	153028718	150419795	0	0
LcClkBypAckTrue_A	153028718	118519	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	150412611	0	0
T1	378518	377810	0	0
T4	182177	181993	0	0
T5	2345	1947	0	0
T15	31061	13664	0	0
T16	1808	1730	0	0
T17	2085	2017	0	0
T18	1041	1025	0	0
T19	1952	1736	0	0
T20	918	875	0	0
T21	1362	1156	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	125703	0	0
T1	378518	156	0	0
T2	0	30	0	0
T3	0	1933	0	0
T4	182177	0	0	0
T5	2345	261	0	0
T9	0	877	0	0
T15	31061	0	0	0
T16	1808	0	0	0
T17	2085	0	0	0
T18	1041	0	0	0
T19	1952	55	0	0
T20	918	0	0	0
T21	1362	0	0	0
T38	0	211	0	0
T60	0	150	0	0
T103	0	117	0	0
T104	0	196	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	150330973	0	2412
T1	378518	377818	0	3
T4	182177	181991	0	3
T5	2345	1860	0	3
T15	31061	13462	0	3
T16	1808	1728	0	3
T17	2085	1831	0	3
T18	1041	1023	0	3
T19	1952	1789	0	3
T20	918	873	0	3
T21	1362	1116	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	202605	0	0
T1	378518	130	0	0
T2	0	71	0	0
T3	0	2461	0	0
T4	182177	0	0	0
T5	2345	346	0	0
T15	31061	0	0	0
T16	1808	0	0	0
T17	2085	184	0	0
T18	1041	0	0	0
T19	1952	0	0	0
T20	918	0	0	0
T21	1362	38	0	0
T38	0	382	0	0
T59	0	56	0	0
T103	0	124	0	0
T104	0	305	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	150419795	0	0
T1	378518	377886	0	0
T4	182177	181993	0	0
T5	2345	1981	0	0
T15	31061	13664	0	0
T16	1808	1730	0	0
T17	2085	2004	0	0
T18	1041	1025	0	0
T19	1952	1791	0	0
T20	918	875	0	0
T21	1362	1122	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	118519	0	0
T1	378518	80	0	0
T2	0	36	0	0
T3	0	1617	0	0
T4	182177	0	0	0
T5	2345	227	0	0
T15	31061	0	0	0
T16	1808	0	0	0
T17	2085	13	0	0
T18	1041	0	0	0
T19	1952	0	0	0
T20	918	0	0	0
T21	1362	34	0	0
T38	0	139	0	0
T59	0	16	0	0
T103	0	58	0	0
T104	0	189	0	0