Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1979737000	16498	0	0
TransStop_A	1979737000	8460	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1979737000	16498	0	0
T1	3936440	95	0	0
T2	0	87	0	0
T3	0	216	0	0
T4	608712	0	0	0
T5	9668	0	0	0
T9	0	225	0	0
T15	125500	0	0	0
T16	14476	0	0	0
T17	8512	0	0	0
T18	18108	4	0	0
T19	8224	0	0	0
T20	20432	4	0	0
T21	5616	0	0	0
T31	0	33	0	0
T51	0	35	0	0
T61	0	4	0	0
T105	0	33	0	0
T106	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1979737000	8460	0	0
T1	3936440	51	0	0
T2	0	47	0	0
T3	0	90	0	0
T4	608712	0	0	0
T5	9668	0	0	0
T9	0	109	0	0
T15	125500	0	0	0
T16	14476	0	0	0
T17	8512	0	0	0
T18	18108	4	0	0
T19	8224	0	0	0
T20	20432	1	0	0
T21	5616	0	0	0
T31	0	22	0	0
T51	0	16	0	0
T61	0	4	0	0
T105	0	22	0	0
T107	0	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	494934250	4071	0	0
TransStop_A	494934250	2077	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494934250	4071	0	0
T1	984110	18	0	0
T2	0	19	0	0
T3	0	52	0	0
T4	152178	0	0	0
T5	2417	0	0	0
T9	0	61	0	0
T15	31375	0	0	0
T16	3619	0	0	0
T17	2128	0	0	0
T18	4527	1	0	0
T19	2056	0	0	0
T20	5108	0	0	0
T21	1404	0	0	0
T31	0	8	0	0
T51	0	11	0	0
T61	0	1	0	0
T105	0	12	0	0
T106	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494934250	2077	0	0
T1	984110	11	0	0
T2	0	10	0	0
T3	0	17	0	0
T4	152178	0	0	0
T5	2417	0	0	0
T9	0	32	0	0
T15	31375	0	0	0
T16	3619	0	0	0
T17	2128	0	0	0
T18	4527	1	0	0
T19	2056	0	0	0
T20	5108	0	0	0
T21	1404	0	0	0
T31	0	6	0	0
T51	0	5	0	0
T61	0	1	0	0
T105	0	8	0	0
T107	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	494934250	4086	0	0
TransStop_A	494934250	2094	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494934250	4086	0	0
T1	984110	23	0	0
T2	0	23	0	0
T3	0	55	0	0
T4	152178	0	0	0
T5	2417	0	0	0
T9	0	51	0	0
T15	31375	0	0	0
T16	3619	0	0	0
T17	2128	0	0	0
T18	4527	1	0	0
T19	2056	0	0	0
T20	5108	1	0	0
T21	1404	0	0	0
T31	0	9	0	0
T51	0	8	0	0
T61	0	1	0	0
T105	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494934250	2094	0	0
T1	984110	16	0	0
T2	0	11	0	0
T3	0	24	0	0
T4	152178	0	0	0
T5	2417	0	0	0
T9	0	25	0	0
T15	31375	0	0	0
T16	3619	0	0	0
T17	2128	0	0	0
T18	4527	1	0	0
T19	2056	0	0	0
T20	5108	0	0	0
T21	1404	0	0	0
T31	0	6	0	0
T51	0	4	0	0
T61	0	1	0	0
T105	0	5	0	0
T107	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	494934250	4189	0	0
TransStop_A	494934250	2155	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494934250	4189	0	0
T1	984110	24	0	0
T2	0	16	0	0
T3	0	58	0	0
T4	152178	0	0	0
T5	2417	0	0	0
T9	0	54	0	0
T15	31375	0	0	0
T16	3619	0	0	0
T17	2128	0	0	0
T18	4527	1	0	0
T19	2056	0	0	0
T20	5108	1	0	0
T21	1404	0	0	0
T31	0	9	0	0
T51	0	7	0	0
T61	0	1	0	0
T105	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494934250	2155	0	0
T1	984110	10	0	0
T2	0	9	0	0
T3	0	27	0	0
T4	152178	0	0	0
T5	2417	0	0	0
T9	0	25	0	0
T15	31375	0	0	0
T16	3619	0	0	0
T17	2128	0	0	0
T18	4527	1	0	0
T19	2056	0	0	0
T20	5108	0	0	0
T21	1404	0	0	0
T31	0	6	0	0
T51	0	2	0	0
T61	0	1	0	0
T105	0	3	0	0
T107	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	494934250	4152	0	0
TransStop_A	494934250	2134	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494934250	4152	0	0
T1	984110	30	0	0
T2	0	29	0	0
T3	0	51	0	0
T4	152178	0	0	0
T5	2417	0	0	0
T9	0	59	0	0
T15	31375	0	0	0
T16	3619	0	0	0
T17	2128	0	0	0
T18	4527	1	0	0
T19	2056	0	0	0
T20	5108	2	0	0
T21	1404	0	0	0
T31	0	7	0	0
T51	0	9	0	0
T61	0	1	0	0
T105	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494934250	2134	0	0
T1	984110	14	0	0
T2	0	17	0	0
T3	0	22	0	0
T4	152178	0	0	0
T5	2417	0	0	0
T9	0	27	0	0
T15	31375	0	0	0
T16	3619	0	0	0
T17	2128	0	0	0
T18	4527	1	0	0
T19	2056	0	0	0
T20	5108	1	0	0
T21	1404	0	0	0
T31	0	4	0	0
T51	0	5	0	0
T61	0	1	0	0
T105	0	6	0	0